ath9k: Configure pll control for AR9485
authorVasanthakumar Thiagarajan <vasanth@atheros.com>
Mon, 6 Dec 2010 12:27:44 +0000 (04:27 -0800)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 7 Dec 2010 21:34:54 +0000 (16:34 -0500)
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/reg.h

index a2f85b7..9f4398c 100644 (file)
@@ -667,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                              struct ath9k_channel *chan)
 {
-       u32 pll = ath9k_hw_compute_pll_control(ah, chan);
+       u32 pll;
+
+       if (AR_SREV_9485(ah))
+               REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
+
+       pll = ath9k_hw_compute_pll_control(ah, chan);
 
        REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
index 0153ba1..d3257f7 100644 (file)
@@ -1114,6 +1114,8 @@ enum {
 #define AR_RTC_PLL_CONTROL \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
 
+#define AR_RTC_PLL_CONTROL2    0x703c
+
 #define AR_RTC_PLL_DIV          0x0000001f
 #define AR_RTC_PLL_DIV_S        0
 #define AR_RTC_PLL_DIV2         0x00000020