+
+/**
+ * Set port up for dma.
+ * @ap: Port to initialize
+ *
+ * Called just after data structures for each port are
+ * initialized. Allocates space for PRD table if the device
+ * is DMA capable SFF.
+
+ Some drivers also use this entry point as a chance to allocate driverprivate
+ memory for ap->private_data.
+
+ *
+ * May be used as the port_start() entry in ata_port_operations.
+ *
+ * LOCKING:
+ * Inherited from caller.
+ */
+static int rdc_pata_port_start(struct ata_port *ap)
+{
+ uint Channel;
+
+ Channel = ap->port_no;
+ dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
+ if (ap->ioaddr.bmdma_addr) {
+ return ata_port_start(ap);
+ } else {
+ dbgprintf("rdc_pata_port_start return 0 !!!\n");
+ return 0;
+ }
+}
+
+static void rdc_pata_port_stop(struct ata_port *ap)
+{
+ uint Channel;
+
+ Channel = ap->port_no;
+
+ dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
+}
+
+/**
+ * prereset for PATA host controller
+ * @link: Target link
+ * @deadline: deadline jiffies for the operation
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
+{
+ struct pci_dev *pdev;
+ struct ata_port *ap;
+ uint Channel;
+
+ dbgprintf("rdc_pata_prereset\n");
+
+ ap = link->ap;
+ pdev = to_pci_dev(ap->host->dev);
+
+ Channel = ap->port_no;
+
+ /* test ATA Decode Enable Bits, should be enable. */
+ if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
+ dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
+ return -ENOENT;
+ } else {
+ dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
+ return ata_std_prereset(link, deadline);
+ }
+}
+
+/**
+ * Probe host controller cable detect info
+ * @ap: Port for which cable detect info is desired
+ *
+ * Read cable indicator from ATA PCI device's PCI config
+ * register. This register is normally set by firmware (BIOS).
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static int rdc_pata_cable_detect(struct ata_port *ap)
+{
+ struct pci_dev *pdev;
+ uint Channel;
+ uint Mask;
+ u32 u32Value;
+
+ dbgprintf("rdc_pata_cable_detect\n");
+
+ pdev = to_pci_dev(ap->host->dev);
+
+ Channel = ap->port_no;
+
+ if (Channel == 0)
+ Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
+ else
+ Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
+
+ /* check BIOS cable detect results */
+ pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
+
+ if ((u32Value & Mask) == 0) {
+ dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
+ return ATA_CBL_PATA40;
+ } else {
+ dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
+ return ATA_CBL_PATA80;
+ }
+}
+
+/**
+ * Initialize host controller PATA PIO timings
+ * @ap: Port whose timings we are configuring
+ * @adev: um
+ *
+ * Set PIO mode for device, in host controller PCI config space.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ struct pci_dev *pdev;
+ uint Channel;
+ uint DeviceID;
+ uint PIOTimingMode;
+ uint PrefetchPostingEnable;
+
+ dbgprintf("rdc_pata_set_piomode\n");
+
+ pdev = to_pci_dev(ap->host->dev);
+
+ Channel = ap->port_no;
+ DeviceID = adev->devno;
+ /*
+ * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
+ * XFER_PIO_2, XFER_PIO_3...
+ */
+ PIOTimingMode = adev->pio_mode - XFER_PIO_0;
+
+ if (adev->class == ATA_DEV_ATA) {
+ PrefetchPostingEnable = TRUE;
+ } else {
+ /* ATAPI, CD DVD Rom */
+ PrefetchPostingEnable = FALSE;
+ }
+
+ /* PIO configuration clears DTE unconditionally. It will be
+ * programmed in set_dmamode which is guaranteed to be called
+ * after set_piomode if any DMA mode is available.
+ */
+
+ /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
+ * selected */
+
+ if (Channel == 0) {
+ ATAHostAdapter_SetPrimaryPIO(
+ pdev,
+ DeviceID,
+ PIOTimingMode,
+ TRUE,/* DMAEnable, */
+ PrefetchPostingEnable
+ );
+
+ ATAHostAdapter_SetPrimaryUDMA(
+ pdev,
+ DeviceID,
+ FALSE,/* UDMAEnable, */
+ UDMA0
+ );
+ } else {
+ ATAHostAdapter_SetSecondaryPIO(
+ pdev,
+ DeviceID,
+ PIOTimingMode,
+ TRUE,/* DMAEnable, */
+ PrefetchPostingEnable
+ );
+
+ ATAHostAdapter_SetSecondaryUDMA(
+ pdev,
+ DeviceID,
+ FALSE,/* UDMAEnable, */
+ UDMA0
+ );
+ }
+ dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
+}
+
+/**
+ * Initialize host controller PATA DMA timings
+ * @ap: Port whose timings we are configuring
+ * @adev: um
+ *
+ * Set MW/UDMA mode for device, in host controller PCI config space.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+ struct pci_dev *pdev;
+ uint Channel;
+ uint DeviceID;
+ uint PIOTimingMode;
+ uint PrefetchPostingEnable;
+ uint DMATimingMode;
+ uint UDMAEnable;
+
+ dbgprintf("rdc_pata_set_dmamode\n");
+
+ pdev = to_pci_dev(ap->host->dev);
+
+ Channel = ap->port_no;
+ DeviceID = adev->devno;
+ PIOTimingMode = adev->pio_mode - XFER_PIO_0; /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
+ DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
+
+ if (adev->class == ATA_DEV_ATA) {
+ PrefetchPostingEnable = TRUE;
+ } else {
+ /* ATAPI, CD DVD Rom */
+ PrefetchPostingEnable = FALSE;
+ }
+
+ if (ap->udma_mask == 0) {
+ /* ata_port dont support udma. depend on hardware spec. */
+ UDMAEnable = FALSE;
+ } else {
+ UDMAEnable = TRUE;
+ }
+
+ /*if (ap->mdma_mask == 0) {
+ }*/
+
+ if (Channel == 0) {
+ if (DMATimingMode >= XFER_UDMA_0) {
+ /* UDMA */
+ ATAHostAdapter_SetPrimaryPIO(pdev,
+ DeviceID,
+ PIOTimingMode,
+ TRUE,/*DMAEnable,*/
+ PrefetchPostingEnable);
+
+ ATAHostAdapter_SetPrimaryUDMA(pdev,
+ DeviceID,
+ UDMAEnable,
+ DMATimingMode - XFER_UDMA_0);
+ dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
+ } else {
+ /* MDMA */
+ ATAHostAdapter_SetPrimaryPIO(pdev,
+ DeviceID,
+ (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
+ TRUE,/*DMAEnable,*/
+ PrefetchPostingEnable);
+
+ ATAHostAdapter_SetPrimaryUDMA(pdev,
+ DeviceID,
+ FALSE,/*UDMAEnable,*/
+ UDMA0);
+ dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
+ }
+ } else {
+ if (DMATimingMode >= XFER_UDMA_0) {
+ /* UDMA */
+ ATAHostAdapter_SetSecondaryPIO(pdev,
+ DeviceID,
+ PIOTimingMode,
+ TRUE,/*DMAEnable,*/
+ PrefetchPostingEnable);
+
+ ATAHostAdapter_SetSecondaryUDMA(pdev,
+ DeviceID,
+ UDMAEnable,
+ DMATimingMode - XFER_UDMA_0);
+ dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
+ } else {
+ /* MDMA */
+ ATAHostAdapter_SetSecondaryPIO(pdev,
+ DeviceID,
+ (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
+ TRUE,/*DMAEnable,*/
+ PrefetchPostingEnable);
+
+ ATAHostAdapter_SetSecondaryUDMA(pdev,
+ DeviceID,
+ FALSE,/*UDMAEnable,*/
+ UDMA0);
+ dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
+ }
+ }
+}
+
+/* pata host template */
+static struct scsi_host_template rdc_pata_sht = {
+ ATA_BMDMA_SHT(DRIVER_NAME),
+};
+
+static const struct ata_port_operations rdc_pata_ops = {
+ .inherits = &ata_bmdma_port_ops,
+
+ .port_start = rdc_pata_port_start,
+ .port_stop = rdc_pata_port_stop,
+ .prereset = rdc_pata_prereset,
+ .cable_detect = rdc_pata_cable_detect,
+ .set_piomode = rdc_pata_set_piomode,
+ .set_dmamode = rdc_pata_set_dmamode,
+};
+
+static struct ata_port_info rdc_pata_port_info[] = {
+ [RDC_17F31011] = {
+ .flags = ATA_FLAG_SLAVE_POSS,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA5, /* udma0-5 */
+ .port_ops = &rdc_pata_ops,
+ },
+
+ [RDC_17F31012] = {
+ .flags = ATA_FLAG_SLAVE_POSS,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA5, /* udma0-5 */
+ .port_ops = &rdc_pata_ops,
+ },
+};
+
+static int __devinit rdc_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ /*struct device *dev = &pdev->dev; */
+ struct ata_port_info port_info[2];
+ const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
+
+ int rc;
+
+ dbgprintf("rdc_init_one\n");
+
+ /* no hotplugging support (FIXME) */ /* why??? */
+ if (!in_module_init) {
+ dbgprintf("rdc_init_one in_module_init == 0 failed \n");
+ return -ENODEV;
+ }
+ port_info[0] = rdc_pata_port_info[ent->driver_data];
+ port_info[1] = rdc_pata_port_info[ent->driver_data];
+
+ /* enable device and prepare host */
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ dbgprintf("rdc_init_one pci_enable_device failed \n");
+ return rc;
+ }
+ /* initialize controller */
+
+ pci_intx(pdev, 1); /* enable interrupt */
+
+ return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
+}
+
+/* a pci driver */
+static struct pci_driver rdc_pata_driver = {
+ .name = DRIVER_NAME,
+ .id_table = rdc_pata_id_table,
+ .probe = rdc_init_one,
+ .remove = ata_pci_remove_one,
+#ifdef CONFIG_PM
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+#endif
+};
+
+static int __init pata_rdc_init(void)
+{
+ int rc;
+
+ dbgprintf("pata_rdc_init\n");
+ rc = pci_register_driver(&rdc_pata_driver);
+ if (rc) {
+ dbgprintf("pata_rdc_init faile\n");
+ return rc;
+ }
+
+ in_module_init = 0;
+
+ return 0;
+}
+
+static void __exit pata_rdc_exit(void)
+{
+ dbgprintf("pata_rdc_exit\n");
+ pci_unregister_driver(&rdc_pata_driver);
+}
+
+module_init(pata_rdc_init);
+module_exit(pata_rdc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("RDC PCI IDE Driver");
+MODULE_VERSION(DRIVER_VERSION);
git.openpandora.org / pandora-kernel.git / commitdiff