Merge branch 'master'

diff --git a/MAINTAINERS b/MAINTAINERS
index e88d193..4788068 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -910,6 +910,15 @@ L: linux-fbdev-devel@lists.sourceforge.net
 W:     http://linux-fbdev.sourceforge.net/
 S:     Maintained
 
+FREESCALE SOC FS_ENET DRIVER
+P:     Pantelis Antoniou
+M:     pantelis.antoniou@gmail.com
+P:     Vitaly Bordug
+M:     vbordug@ru.mvista.com
+L:     linuxppc-embedded@ozlabs.org
+L:     netdev@vger.kernel.org
+S:     Maintained
+
 FILE LOCKING (flock() and fcntl()/lockf())
 P:     Matthew Wilcox
 M:     matthew@wil.cx

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6d4f9ce..97760c1 100644 (file)
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1203,7 +1203,7 @@ config IBM_EMAC_RX_SKB_HEADROOM
 
 config IBM_EMAC_PHY_RX_CLK_FIX
        bool "PHY Rx clock workaround"
-       depends on IBM_EMAC && (405EP || 440GX || 440EP)
+       depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
        help
          Enable this if EMAC attached to a PHY which doesn't generate
          RX clock if there is no link, if this is the case, you will 

diff --git a/drivers/net/fec_8xx/Kconfig b/drivers/net/fec_8xx/Kconfig
index db36ac3..4560026 100644 (file)
--- a/drivers/net/fec_8xx/Kconfig
+++ b/drivers/net/fec_8xx/Kconfig
@@ -1,6 +1,6 @@
 config FEC_8XX
        tristate "Motorola 8xx FEC driver"
-       depends on NET_ETHERNET && 8xx && (NETTA || NETPHONE)
+       depends on NET_ETHERNET
        select MII
 
 config FEC_8XX_GENERIC_PHY
@@ -12,3 +12,9 @@ config FEC_8XX_DM9161_PHY
        bool "Support DM9161 PHY"
        depends on FEC_8XX
        default n
+
+config FEC_8XX_LXT971_PHY
+       bool "Support LXT971/LXT972 PHY"
+       depends on FEC_8XX
+       default n
+

diff --git a/drivers/net/fec_8xx/fec_mii.c b/drivers/net/fec_8xx/fec_mii.c
index 803eb09..3b44ac1 100644 (file)
--- a/drivers/net/fec_8xx/fec_mii.c
+++ b/drivers/net/fec_8xx/fec_mii.c
@@ -203,6 +203,39 @@ static void dm9161_shutdown(struct net_device *dev)
 
 #endif
 
+#ifdef CONFIG_FEC_8XX_LXT971_PHY
+
+/* Support for LXT971/972 PHY */
+
+#define MII_LXT971_PCR         16 /* Port Control Register */
+#define MII_LXT971_SR2         17 /* Status Register 2 */
+#define MII_LXT971_IER         18 /* Interrupt Enable Register */
+#define MII_LXT971_ISR         19 /* Interrupt Status Register */
+#define MII_LXT971_LCR         20 /* LED Control Register */
+#define MII_LXT971_TCR         30 /* Transmit Control Register */
+
+static void lxt971_startup(struct net_device *dev)
+{
+       struct fec_enet_private *fep = netdev_priv(dev);
+
+       fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x00F2);
+}
+
+static void lxt971_ack_int(struct net_device *dev)
+{
+       struct fec_enet_private *fep = netdev_priv(dev);
+
+       fec_mii_read(dev, fep->mii_if.phy_id, MII_LXT971_ISR);
+}
+
+static void lxt971_shutdown(struct net_device *dev)
+{
+       struct fec_enet_private *fep = netdev_priv(dev);
+
+       fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x0000);
+}
+#endif
+
 /**********************************************************************************/
 
 static const struct phy_info phy_info[] = {
@@ -215,6 +248,15 @@ static const struct phy_info phy_info[] = {
         .shutdown = dm9161_shutdown,
         },
 #endif
+#ifdef CONFIG_FEC_8XX_LXT971_PHY
+       {
+        .id = 0x0001378e,
+        .name = "LXT971/972",
+        .startup = lxt971_startup,
+        .ack_int = lxt971_ack_int,
+        .shutdown = lxt971_shutdown,
+       },
+#endif
 #ifdef CONFIG_FEC_8XX_GENERIC_PHY
        {
         .id = 0,

diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index 44fac73..9342d5b 100644 (file)
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -130,7 +130,7 @@ static int fs_enet_rx_napi(struct net_device *dev, int *budget)
 
                        skb = fep->rx_skbuff[curidx];
 
-                       dma_unmap_single(fep->dev, skb->data,
+                       dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
                                L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
                                DMA_FROM_DEVICE);
 
@@ -144,7 +144,7 @@ static int fs_enet_rx_napi(struct net_device *dev, int *budget)
 
                        skb = fep->rx_skbuff[curidx];
 
-                       dma_unmap_single(fep->dev, skb->data,
+                       dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
                                L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
                                DMA_FROM_DEVICE);
 
@@ -268,7 +268,7 @@ static int fs_enet_rx_non_napi(struct net_device *dev)
 
                        skb = fep->rx_skbuff[curidx];
 
-                       dma_unmap_single(fep->dev, skb->data,
+                       dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
                                L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
                                DMA_FROM_DEVICE);
 
@@ -278,7 +278,7 @@ static int fs_enet_rx_non_napi(struct net_device *dev)
 
                        skb = fep->rx_skbuff[curidx];
 
-                       dma_unmap_single(fep->dev, skb->data,
+                       dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
                                L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
                                DMA_FROM_DEVICE);
 
@@ -399,7 +399,8 @@ static void fs_enet_tx(struct net_device *dev)
                        fep->stats.collisions++;
 
                /* unmap */
-               dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
+               dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
+                               skb->len, DMA_TO_DEVICE);
 
                /*
                 * Free the sk buffer associated with this last transmit. 
@@ -547,17 +548,19 @@ void fs_cleanup_bds(struct net_device *dev)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
        struct sk_buff *skb;
+       cbd_t *bdp;
        int i;
 
        /*
         * Reset SKB transmit buffers.  
         */
-       for (i = 0; i < fep->tx_ring; i++) {
+       for (i = 0, bdp = fep->tx_bd_base; i < fep->tx_ring; i++, bdp++) {
                if ((skb = fep->tx_skbuff[i]) == NULL)
                        continue;
 
                /* unmap */
-               dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
+               dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
+                               skb->len, DMA_TO_DEVICE);
 
                fep->tx_skbuff[i] = NULL;
                dev_kfree_skb(skb);
@@ -566,12 +569,12 @@ void fs_cleanup_bds(struct net_device *dev)
        /*
         * Reset SKB receive buffers 
         */
-       for (i = 0; i < fep->rx_ring; i++) {
+       for (i = 0, bdp = fep->rx_bd_base; i < fep->rx_ring; i++, bdp++) {
                if ((skb = fep->rx_skbuff[i]) == NULL)
                        continue;
 
                /* unmap */
-               dma_unmap_single(fep->dev, skb->data,
+               dma_unmap_single(fep->dev, CBDR_BUFADDR(bdp),
                        L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
                        DMA_FROM_DEVICE);
 

diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
index 28c476f..644edbf 100644 (file)
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ b/drivers/net/ibm_emac/ibm_emac.h
@@ -26,7 +26,8 @@
 /* This is a simple check to prevent use of this driver on non-tested SoCs */
 #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
     !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
-    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H)
+    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440GR)
 #error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
 #endif
 
@@ -246,6 +247,25 @@ struct emac_regs {
 #define EMAC_STACR_PCDA_SHIFT          5
 #define EMAC_STACR_PRA_MASK            0x1f
 
+/*
+ * For the 440SPe, AMCC inexplicably changed the polarity of
+ * the "operation complete" bit in the MII control register.
+ */
+#if defined(CONFIG_440SPE)
+static inline int emac_phy_done(u32 stacr)
+{
+       return !(stacr & EMAC_STACR_OC);
+};
+#define EMAC_STACR_START               EMAC_STACR_OC
+
+#else /* CONFIG_440SPE */
+static inline int emac_phy_done(u32 stacr)
+{
+       return stacr & EMAC_STACR_OC;
+};
+#define EMAC_STACR_START               0
+#endif /* !CONFIG_440SPE */
+
 /* EMACx_TRTR */
 #if !defined(CONFIG_IBM_EMAC4)
 #define EMAC_TRTR_SHIFT                        27

diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
index 943fbd1..eb7d694 100644 (file)
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ b/drivers/net/ibm_emac/ibm_emac_core.c
@@ -87,10 +87,11 @@ MODULE_LICENSE("GPL");
  */
 static u32 busy_phy_map;
 
-#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP))
+#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
+    (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
 /* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
  * with PHY RX clock problem.
- * 440EP has more sane SDR0_MFR register implementation than 440GX, which
+ * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
  * also allows controlling each EMAC clock
  */
 static inline void EMAC_RX_CLK_TX(int idx)
@@ -100,7 +101,7 @@ static inline void EMAC_RX_CLK_TX(int idx)
 
 #if defined(CONFIG_405EP)
        mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
-#else /* CONFIG_440EP */
+#else /* CONFIG_440EP || CONFIG_440GR */
        SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
 #endif
 
@@ -546,7 +547,7 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
 
        /* Wait for management interface to become idle */
        n = 10;
-       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
+       while (!emac_phy_done(in_be32(&p->stacr))) {
                udelay(1);
                if (!--n)
                        goto to;
@@ -556,11 +557,12 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
        out_be32(&p->stacr,
                 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
                 (reg & EMAC_STACR_PRA_MASK)
-                | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT));
+                | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
+                | EMAC_STACR_START);
 
        /* Wait for read to complete */
        n = 100;
-       while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) {
+       while (!emac_phy_done(r = in_be32(&p->stacr))) {
                udelay(1);
                if (!--n)
                        goto to;
@@ -594,7 +596,7 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
 
        /* Wait for management interface to be idle */
        n = 10;
-       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
+       while (!emac_phy_done(in_be32(&p->stacr))) {
                udelay(1);
                if (!--n)
                        goto to;
@@ -605,11 +607,11 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
                 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
                 (reg & EMAC_STACR_PRA_MASK) |
                 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
-                (val << EMAC_STACR_PHYD_SHIFT));
+                (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
 
        /* Wait for write to complete */
        n = 100;
-       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
+       while (!emac_phy_done(in_be32(&p->stacr))) {
                udelay(1);
                if (!--n)
                        goto to;

diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
index 15b0bda..2a2d3b2 100644 (file)
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ b/drivers/net/ibm_emac/ibm_emac_mal.h
@@ -32,9 +32,10 @@
  * reflect the fact that 40x and 44x have slightly different MALs. --ebs
  */
 #if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
-    defined(CONFIG_440EP) || defined(CONFIG_NP405H)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
 #define MAL_VERSION            1
-#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+      defined(CONFIG_440SPE)
 #define MAL_VERSION            2
 #else
 #error "Unknown SoC, please check chip manual and choose MAL 'version'"

diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
index a27e49c..67935dd 100644 (file)
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ b/drivers/net/ibm_emac/ibm_emac_phy.c
@@ -236,12 +236,16 @@ static struct mii_phy_def genmii_phy_def = {
 };
 
 /* CIS8201 */
+#define MII_CIS8201_10BTCSR    0x16
+#define  TENBTCSR_ECHO_DISABLE 0x2000
 #define MII_CIS8201_EPCR       0x17
 #define  EPCR_MODE_MASK                0x3000
 #define  EPCR_GMII_MODE                0x0000
 #define  EPCR_RGMII_MODE       0x1000
 #define  EPCR_TBI_MODE         0x2000
 #define  EPCR_RTBI_MODE                0x3000
+#define MII_CIS8201_ACSR       0x1c
+#define  ACSR_PIN_PRIO_SELECT  0x0004
 
 static int cis8201_init(struct mii_phy *phy)
 {
@@ -269,6 +273,14 @@ static int cis8201_init(struct mii_phy *phy)
        }
 
        phy_write(phy, MII_CIS8201_EPCR, epcr);
+       
+       /* MII regs override strap pins */
+       phy_write(phy, MII_CIS8201_ACSR, 
+                 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
+
+       /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
+       phy_write(phy, MII_CIS8201_10BTCSR,
+                 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
 
        return 0;
 }