Blackfin arch: move async memory programming into common setup_arch() as the banks...

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 23e637e..15967e7 100644 (file)
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -738,6 +738,16 @@ void __init setup_arch(char **cmdline_p)
 
        memory_setup();
 
+       /* Initialize Async memory banks */
+       bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
+       bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
+       bfin_write_EBIU_AMGCTL(AMGCTLVAL);
+#ifdef CONFIG_EBIU_MBSCTLVAL
+       bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
+       bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
+       bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
+#endif
+
        cclk = get_cclk();
        sclk = get_sclk();
 

diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index 180d3c8..9173dce 100644 (file)
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -170,28 +170,6 @@ ENTRY(__start)
        call _start_dma_code;
 #endif
 
-       /* Code for initializing Async memory banks */
-
-       p2.h = hi(EBIU_AMBCTL1);
-       p2.l = lo(EBIU_AMBCTL1);
-       r0.h = hi(AMBCTL1VAL);
-       r0.l = lo(AMBCTL1VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMBCTL0);
-       p2.l = lo(EBIU_AMBCTL0);
-       r0.h = hi(AMBCTL0VAL);
-       r0.l = lo(AMBCTL0VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMGCTL);
-       p2.l = lo(EBIU_AMGCTL);
-       r0 = AMGCTLVAL;
-       w[p2] = r0;
-       ssync;
-
        /* This section keeps the processor in supervisor mode
         * during kernel boot.  Switches to user mode at end of boot.
         * See page 3-9 of Hardware Reference manual for documentation.

diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 0ffbe7a..7f0a7a0 100644 (file)
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -172,28 +172,6 @@ ENTRY(__start)
        call _start_dma_code;
 #endif
 
-       /* Code for initializing Async memory banks */
-
-       p2.h = hi(EBIU_AMBCTL1);
-       p2.l = lo(EBIU_AMBCTL1);
-       r0.h = hi(AMBCTL1VAL);
-       r0.l = lo(AMBCTL1VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMBCTL0);
-       p2.l = lo(EBIU_AMBCTL0);
-       r0.h = hi(AMBCTL0VAL);
-       r0.l = lo(AMBCTL0VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMGCTL);
-       p2.l = lo(EBIU_AMGCTL);
-       r0 = AMGCTLVAL;
-       w[p2] = r0;
-       ssync;
-
        /* This section keeps the processor in supervisor mode
         * during kernel boot.  Switches to user mode at end of boot.
         * See page 3-9 of Hardware Reference manual for documentation.

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index c11f0fd..c062acb 100644 (file)
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -184,28 +184,6 @@ ENTRY(__start)
        call _start_dma_code;
 #endif
 
-       /* Code for initializing Async memory banks */
-
-       p2.h = hi(EBIU_AMBCTL1);
-       p2.l = lo(EBIU_AMBCTL1);
-       r0.h = hi(AMBCTL1VAL);
-       r0.l = lo(AMBCTL1VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMBCTL0);
-       p2.l = lo(EBIU_AMBCTL0);
-       r0.h = hi(AMBCTL0VAL);
-       r0.l = lo(AMBCTL0VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMGCTL);
-       p2.l = lo(EBIU_AMGCTL);
-       r0 = AMGCTLVAL;
-       w[p2] = r0;
-       ssync;
-
        /* This section keeps the processor in supervisor mode
         * during kernel boot.  Switches to user mode at end of boot.
         * See page 3-9 of Hardware Reference manual for documentation.

diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 96fbdb7..832a8d7 100644 (file)
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -133,48 +133,6 @@ ENTRY(__start)
 #ifdef CONFIG_BFIN_KERNEL_CLOCK
        call _start_dma_code;
 #endif
-       /* Code for initializing Async memory banks */
-
-       p2.h = hi(EBIU_AMBCTL1);
-       p2.l = lo(EBIU_AMBCTL1);
-       r0.h = hi(AMBCTL1VAL);
-       r0.l = lo(AMBCTL1VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMBCTL0);
-       p2.l = lo(EBIU_AMBCTL0);
-       r0.h = hi(AMBCTL0VAL);
-       r0.l = lo(AMBCTL0VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMGCTL);
-       p2.l = lo(EBIU_AMGCTL);
-       r0 = AMGCTLVAL;
-       w[p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_MBSCTL);
-       p2.l = lo(EBIU_MBSCTL);
-       r0.h = hi(CONFIG_EBIU_MBSCTLVAL);
-       r0.l = lo(CONFIG_EBIU_MBSCTLVAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_MODE);
-       p2.l = lo(EBIU_MODE);
-       r0.h = hi(CONFIG_EBIU_MODEVAL);
-       r0.l = lo(CONFIG_EBIU_MODEVAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_FCTL);
-       p2.l = lo(EBIU_FCTL);
-       r0.h = hi(CONFIG_EBIU_FCTLVAL);
-       r0.l = lo(CONFIG_EBIU_FCTLVAL);
-       [p2] = r0;
-       ssync;
 
        /* This section keeps the processor in supervisor mode
         * during kernel boot.  Switches to user mode at end of boot.

diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 553b2d1..c541b31 100644 (file)
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -161,28 +161,6 @@ ENTRY(__start)
        call _start_dma_code;
 #endif
 
-       /* Code for initializing Async memory banks */
-
-       p2.h = hi(EBIU_AMBCTL1);
-       p2.l = lo(EBIU_AMBCTL1);
-       r0.h = hi(AMBCTL1VAL);
-       r0.l = lo(AMBCTL1VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMBCTL0);
-       p2.l = lo(EBIU_AMBCTL0);
-       r0.h = hi(AMBCTL0VAL);
-       r0.l = lo(AMBCTL0VAL);
-       [p2] = r0;
-       ssync;
-
-       p2.h = hi(EBIU_AMGCTL);
-       p2.l = lo(EBIU_AMGCTL);
-       r0 = AMGCTLVAL;
-       w[p2] = r0;
-       ssync;
-
        /* This section keeps the processor in supervisor mode
         * during kernel boot.  Switches to user mode at end of boot.
         * See page 3-9 of Hardware Reference manual for documentation.