drm/i915: Set SSC frequency for 8xx chips correctly

All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 716409a..da22863 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
                dev_priv->lvds_use_ssc = general->enable_ssc;
 
                if (dev_priv->lvds_use_ssc) {
-                 if (IS_I855(dev_priv->dev))
-                   dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
-                 else
-                   dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+                       if (IS_I85X(dev_priv->dev))
+                               dev_priv->lvds_ssc_freq =
+                                       general->ssc_freq ? 66 : 48;
+                       else
+                               dev_priv->lvds_ssc_freq =
+                                       general->ssc_freq ? 100 : 96;
                }
        }
 }