Merge branches 'amba', 'fixes', 'kees', 'misc' and 'unstable/sa11x0' into for-next

diff --cc arch/arm/Kconfig.debug
Simple merge

diff --cc arch/arm/include/asm/pgtable.h
Simple merge

diff --cc arch/arm/kernel/traps.c
Simple merge

diff --cc arch/arm/mach-footbridge/dc21285-timer.c
index 9ee78f7,9ee78f7,782f6c7,9ee78f7,2babdbc,9ee78f7..3971104
--- 1/arch/arm/mach-footbridge/dc21285-timer.c
--- 2/arch/arm/mach-footbridge/dc21285-timer.c
--- 3/arch/arm/mach-footbridge/dc21285-timer.c
--- 4/arch/arm/mach-footbridge/dc21285-timer.c
--- 5/arch/arm/mach-footbridge/dc21285-timer.c
--- 6/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@@@@@@ -102,5 -102,5 -103,5 -102,5 -121,21 -102,5 +122,21 @@@@@@@ void __init footbridge_timer_init(void
        setup_irq(ce->irq, &footbridge_timer_irq);
      
        ce->cpumask = cpumask_of(smp_processor_id());
-- ---  clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
++ +++  clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
++ + +}
++++ +
++++ +static u32 notrace footbridge_read_sched_clock(void)
++++ +{
++++ +  return ~*CSR_TIMER3_VALUE;
++++ +}
++++ +
++++ +void __init footbridge_sched_clock(void)
++++ +{
++++ +  unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
++++ +
++++ +  *CSR_TIMER3_LOAD = 0;
++++ +  *CSR_TIMER3_CLR = 0;
++++ +  *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
++++ +
++++ +  setup_sched_clock(footbridge_read_sched_clock, 24, rate);
  +   }

diff --cc arch/arm/mach-highbank/highbank.c
Simple merge

diff --cc arch/arm/mach-omap2/omap4-common.c
Simple merge

diff --cc arch/arm/mm/dma-mapping.c
index f61a570,79f8b39,f61a570,f0ea013,f61a570,f6b6bfa..1a77450
--- 1/arch/arm/mm/dma-mapping.c
--- 2/arch/arm/mm/dma-mapping.c
--- 3/arch/arm/mm/dma-mapping.c
--- 4/arch/arm/mm/dma-mapping.c
--- 5/arch/arm/mm/dma-mapping.c
--- 6/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@@@@@@ -212,8 -173,32 -212,8 -173,32 -212,8 -176,34 +212,8 @@@@@@@ static u64 get_coherent_dma_mask(struc
                        return 0;
                }
      
     -          max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
     -
 - - -          /*
 - - -           * If the mask allows for more memory than we can address,
 - - -           * and we actually have that much memory, then fail the
 - - -           * allocation.
 - - -           */
 - - -          if (sizeof(mask) != sizeof(dma_addr_t) &&
 - - -              mask > (dma_addr_t)~0 &&
 - -                dma_to_pfn(dev, ~0) > arm_dma_pfn_limit) {
     -              dma_to_pfn(dev, ~0) > max_dma_pfn) {
 - - -                  dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
 - - -                           mask);
 - - -                  dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
 - - -                  return 0;
 - - -          }
 - - -
 - - -          /*
 - - -           * Now check that the mask, when translated to a PFN,
 - - -           * fits within the allowable addresses which we can
 - - -           * allocate.
 - - -           */
 - -            if (dma_to_pfn(dev, mask) < arm_dma_pfn_limit) {
     -          if (dma_to_pfn(dev, mask) < max_dma_pfn) {
 - - -                  dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
 - - -                           mask,
 - - -                           dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
 - - -                           arm_dma_pfn_limit + 1);
 + + +          if (!__dma_supported(dev, mask, true))
                        return 0;
 - - -          }
        }
      
        return mask;