First step of modularizing ECC support.
- Move ECC related functionality into a seperate embedded data structure
- Get rid of the hardware dependend constants to simplify new ECC models
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
}
/* 25 us command delay time */
this->chip_delay = 30;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Set chip enabled, but */
ams_delta_latch2_write(NAND_MASK, AMS_DELTA_LATCH2_NAND_NRE |
/* 30 us command delay time */
this->chip_delay = 30;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
this->options = NAND_NO_AUTOINCR;
this->dev_ready = autcpu12_device_ready;
/* 20 us command delay time */
this->chip_delay = 20;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Enable the following for a flash based bad block table */
/*
this->chip_delay = 0;
- this->eccmode = NAND_ECC_HW3_256;
- this->enable_hwecc = cs_enable_hwecc;
- this->calculate_ecc = cs_calculate_ecc;
- this->correct_data = nand_correct_data;
-
+ this->ecc.mode = NAND_ECC_HW;
+ this->ecc.size = 256;
+ this->ecc.bytes = 3;
+ this->ecc.hwctl = cs_enable_hwecc;
+ this->ecc.calculate = cs_calculate_ecc;
+ this->ecc.correct = nand_correct_data;
+
/* Enable the following for a flash based bad block table */
this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;
nand->dev_ready = doc200x_dev_ready;
nand->waitfunc = doc200x_wait;
nand->block_bad = doc200x_block_bad;
- nand->enable_hwecc = doc200x_enable_hwecc;
- nand->calculate_ecc = doc200x_calculate_ecc;
- nand->correct_data = doc200x_correct_data;
+ nand->ecc.hwctl = doc200x_enable_hwecc;
+ nand->ecc.calculate = doc200x_calculate_ecc;
+ nand->ecc.correct = doc200x_correct_data;
nand->autooob = &doc200x_oobinfo;
- nand->eccmode = NAND_ECC_HW6_512;
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 6;
nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME;
doc->physadr = physadr;
this->dev_ready = NULL; /* unknown whether that was correct or not so we will just do it like this */
/* 15 us command delay time */
this->chip_delay = 50;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
this->options = NAND_NO_AUTOINCR;
/* Scan to find existence of the device */
{
int i, status;
uint8_t ecc_code[32];
- int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
+ int eccmode = oobsel->useecc ? this->ecc.mode : NAND_ECC_NONE;
int *oob_config = oobsel->eccpos;
- int datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
+ int datidx = 0, eccidx = 0, eccsteps = this->ecc.steps;
int eccbytes = 0;
/* FIXME: Enable cached programming */
/* Software ecc 3/256, write all */
case NAND_ECC_SOFT:
for (; eccsteps; eccsteps--) {
- this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
+ this->ecc.calculate(mtd, &this->data_poi[datidx], ecc_code);
for (i = 0; i < 3; i++, eccidx++)
oob_buf[oob_config[eccidx]] = ecc_code[i];
- datidx += this->eccsize;
+ datidx += this->ecc.size;
}
this->write_buf(mtd, this->data_poi, mtd->oobblock);
break;
default:
- eccbytes = this->eccbytes;
+ eccbytes = this->ecc.bytes;
for (; eccsteps; eccsteps--) {
/* enable hardware ecc logic for write */
- this->enable_hwecc(mtd, NAND_ECC_WRITE);
- this->write_buf(mtd, &this->data_poi[datidx], this->eccsize);
- this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code);
+ this->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ this->write_buf(mtd, &this->data_poi[datidx], this->ecc.size);
+ this->ecc.calculate(mtd, &this->data_poi[datidx], ecc_code);
for (i = 0; i < eccbytes; i++, eccidx++)
oob_buf[oob_config[eccidx]] = ecc_code[i];
/* If the hardware ecc provides syndromes then
* the data bytes (words) */
if (this->options & NAND_HWECC_SYNDROME)
this->write_buf(mtd, ecc_code, eccbytes);
- datidx += this->eccsize;
+ datidx += this->ecc.size;
}
break;
}
if (oobsel->useecc == MTD_NANDECC_AUTOPLACE)
oobsel = this->autooob;
- eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
+ eccmode = oobsel->useecc ? this->ecc.mode : NAND_ECC_NONE;
oob_config = oobsel->eccpos;
/* Select the NAND device */
col = from & (mtd->oobblock - 1);
end = mtd->oobblock;
- ecc = this->eccsize;
- eccbytes = this->eccbytes;
+ ecc = this->ecc.size;
+ eccbytes = this->ecc.bytes;
if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME))
compareecc = 0;
oobsel->useecc == MTD_NANDECC_AUTOPL_USR)
oob_data = &this->data_buf[end];
- eccsteps = this->eccsteps;
+ eccsteps = this->ecc.steps;
switch (eccmode) {
case NAND_ECC_NONE:{
case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
this->read_buf(mtd, data_poi, end);
for (i = 0, datidx = 0; eccsteps; eccsteps--, i += 3, datidx += ecc)
- this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
+ this->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
break;
default:
for (i = 0, datidx = 0; eccsteps; eccsteps--, i += eccbytes, datidx += ecc) {
- this->enable_hwecc(mtd, NAND_ECC_READ);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
this->read_buf(mtd, &data_poi[datidx], ecc);
/* HW ecc with syndrome calculation must read the
if (!compareecc) {
/* Some hw ecc generators need to know when the
* syndrome is read from flash */
- this->enable_hwecc(mtd, NAND_ECC_READSYN);
+ this->ecc.hwctl(mtd, NAND_ECC_READSYN);
this->read_buf(mtd, &oob_data[i], eccbytes);
/* We calc error correction directly, it checks the hw
* generator for an error, reads back the syndrome and
* does the error correction on the fly */
- ecc_status = this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]);
+ ecc_status = this->ecc.correct(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]);
if ((ecc_status == -1) || (ecc_status > (flags && 0xff))) {
DEBUG(MTD_DEBUG_LEVEL0, "nand_read_ecc: "
"Failed ECC read, page 0x%08x on chip %d\n", page, chipnr);
ecc_failed++;
}
} else {
- this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]);
+ this->ecc.calculate(mtd, &data_poi[datidx], &ecc_calc[i]);
}
}
break;
ecc_code[j] = oob_data[oob_config[j]];
/* correct data, if necessary */
- for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) {
- ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
+ for (i = 0, j = 0, datidx = 0; i < this->ecc.steps; i++, datidx += ecc) {
+ ecc_status = this->ecc.correct(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]);
/* Get next chunk of ecc bytes */
j += eccbytes;
break;
case MTD_NANDECC_PLACE:
/* YAFFS1 legacy mode */
- oob_data += this->eccsteps * sizeof(int);
+ oob_data += this->ecc.steps * sizeof(int);
default:
oob_data += mtd->oobsize;
}
* check ECC mode, default to software if 3byte/512byte hardware ECC is
* selected and we have 256 byte pagesize fallback to software ECC
*/
- this->eccsize = 256;
- this->eccbytes = 3;
-
- switch (this->eccmode) {
- case NAND_ECC_HW12_2048:
- if (mtd->oobblock < 2048) {
- printk(KERN_WARNING "2048 byte HW ECC not possible on "
- "%d byte page size, fallback to SW ECC\n",
- mtd->oobblock);
- this->eccmode = NAND_ECC_SOFT;
- this->calculate_ecc = nand_calculate_ecc;
- this->correct_data = nand_correct_data;
- } else
- this->eccsize = 2048;
- break;
-
- case NAND_ECC_HW3_512:
- case NAND_ECC_HW6_512:
- case NAND_ECC_HW8_512:
- if (mtd->oobblock == 256) {
- printk(KERN_WARNING "512 byte HW ECC not possible on "
- "256 Byte pagesize, fallback to SW ECC \n");
- this->eccmode = NAND_ECC_SOFT;
- this->calculate_ecc = nand_calculate_ecc;
- this->correct_data = nand_correct_data;
- } else
- this->eccsize = 512; /* set eccsize to 512 */
- break;
+ switch (this->ecc.mode) {
+ case NAND_ECC_HW:
+ case NAND_ECC_HW_SYNDROME:
+ if (!this->ecc.calculate || !this->ecc.correct ||
+ !this->ecc.hwctl) {
+ printk(KERN_WARNING "No ECC functions supplied, "
+ "Hardware ECC not possible\n");
+ BUG();
+ }
+ if (mtd->oobblock >= this->ecc.size)
+ break;
+ printk(KERN_WARNING "%d byte HW ECC not possible on "
+ "%d byte page size, fallback to SW ECC\n",
+ this->ecc.size, mtd->oobblock);
+ this->ecc.mode = NAND_ECC_SOFT;
- case NAND_ECC_HW3_256:
+ case NAND_ECC_SOFT:
+ this->ecc.calculate = nand_calculate_ecc;
+ this->ecc.correct = nand_correct_data;
+ this->ecc.size = 256;
+ this->ecc.bytes = 3;
break;
case NAND_ECC_NONE:
printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
"This is not recommended !!\n");
- this->eccmode = NAND_ECC_NONE;
+ this->ecc.size = mtd->oobblock;
+ this->ecc.bytes = 0;
break;
-
- case NAND_ECC_SOFT:
- this->calculate_ecc = nand_calculate_ecc;
- this->correct_data = nand_correct_data;
- break;
-
default:
printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
- this->eccmode);
- BUG();
- }
-
- /*
- * Check hardware ecc function availability and adjust number of ecc
- * bytes per calculation step
- */
- switch (this->eccmode) {
- case NAND_ECC_HW12_2048:
- this->eccbytes += 4;
- case NAND_ECC_HW8_512:
- this->eccbytes += 2;
- case NAND_ECC_HW6_512:
- this->eccbytes += 3;
- case NAND_ECC_HW3_512:
- case NAND_ECC_HW3_256:
- if (this->calculate_ecc && this->correct_data &&
- this->enable_hwecc)
- break;
- printk(KERN_WARNING "No ECC functions supplied, "
- "Hardware ECC not possible\n");
+ this->ecc.mode);
BUG();
}
- mtd->eccsize = this->eccsize;
-
/*
* Set the number of read / write steps for one page depending on ECC
* mode
*/
- switch (this->eccmode) {
- case NAND_ECC_HW12_2048:
- this->eccsteps = mtd->oobblock / 2048;
- break;
- case NAND_ECC_HW3_512:
- case NAND_ECC_HW6_512:
- case NAND_ECC_HW8_512:
- this->eccsteps = mtd->oobblock / 512;
- break;
- case NAND_ECC_HW3_256:
- case NAND_ECC_SOFT:
- this->eccsteps = mtd->oobblock / 256;
- break;
-
- case NAND_ECC_NONE:
- this->eccsteps = 1;
- break;
+ this->ecc.steps = mtd->oobblock / this->ecc.size;
+ if(this->ecc.steps * this->ecc.size != mtd->oobblock) {
+ printk(KERN_WARNING "Invalid ecc parameters\n");
+ BUG();
}
/* Initialize state, waitqueue and spinlock */
chip->verify_buf = ns_nand_verify_buf;
chip->write_word = ns_nand_write_word;
chip->read_word = ns_nand_read_word;
- chip->eccmode = NAND_ECC_SOFT;
+ chip->ecc.mode = NAND_ECC_SOFT;
chip->options |= NAND_SKIP_BBTSCAN;
/*
chip->read_buf = ndfc_read_buf;
chip->write_buf = ndfc_write_buf;
chip->verify_buf = ndfc_verify_buf;
- chip->correct_data = nand_correct_data;
- chip->enable_hwecc = ndfc_enable_hwecc;
- chip->calculate_ecc = ndfc_calculate_ecc;
- chip->eccmode = NAND_ECC_HW3_256;
+ chip->ecc.correct = nand_correct_data;
+ chip->ecc.hwctl = ndfc_enable_hwecc;
+ chip->ecc.calculate = ndfc_calculate_ecc;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = 256;
+ chip->ecc.bytes = 3;
chip->autooob = mtd->pl_chip->autooob;
mtd->mtd.priv = chip;
mtd->mtd.owner = THIS_MODULE;
#endif
this->chip_delay = NAND_BIG_DELAY_US;
/* ECC mode */
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Scan to find existence of the device (it could not be mounted) */
if (nand_scan(ppchameleon_mtd, 1)) {
this->chip_delay = NAND_SMALL_DELAY_US;
/* ECC mode */
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Scan to find existence of the device */
if (nand_scan(ppchameleonevb_mtd, 1)) {
#ifdef RTC_FROM4_HWECC
printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
- this->eccmode = NAND_ECC_HW8_512;
+ this->ecc.mode = NAND_ECC_HW_SYNDROME;
+ this->ecc.size = 512;
+ this->ecc.bytes = 8;
this->options |= NAND_HWECC_SYNDROME;
/* return the status of extra status and ECC checks */
this->errstat = rtc_from4_errstat;
/* set the nand_oobinfo to support FPGA H/W error detection */
this->autooob = &rtc_from4_nand_oobinfo;
- this->enable_hwecc = rtc_from4_enable_hwecc;
- this->calculate_ecc = rtc_from4_calculate_ecc;
- this->correct_data = rtc_from4_correct_data;
+ this->ecc.hwctl = rtc_from4_enable_hwecc;
+ this->ecc.calculate = rtc_from4_calculate_ecc;
+ this->ecc.correct = rtc_from4_correct_data;
#else
printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
#endif
/* set the bad block tables to support debugging */
nmtd->set = set;
if (hardware_ecc) {
- chip->correct_data = s3c2410_nand_correct_data;
- chip->enable_hwecc = s3c2410_nand_enable_hwecc;
- chip->calculate_ecc = s3c2410_nand_calculate_ecc;
- chip->eccmode = NAND_ECC_HW3_512;
+ chip->ecc.correct = s3c2410_nand_correct_data;
+ chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
+ chip->ecc.calculate = s3c2410_nand_calculate_ecc;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = 512;
+ chip->ecc.bytes = 3;
chip->autooob = &nand_hw_eccoob;
if (info->is_s3c2440) {
- chip->enable_hwecc = s3c2440_nand_enable_hwecc;
- chip->calculate_ecc = s3c2440_nand_calculate_ecc;
+ chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
+ chip->ecc.calculate = s3c2440_nand_calculate_ecc;
}
} else {
- chip->eccmode = NAND_ECC_SOFT;
+ chip->ecc.mode = NAND_ECC_SOFT;
}
}
/* 15 us command delay time */
this->chip_delay = 15;
/* set eccmode using hardware ECC */
- this->eccmode = NAND_ECC_HW3_256;
+ this->ecc.mode = NAND_ECC_HW;
+ this->ecc.size = 256;
+ this->ecc.bytes = 3;
this->badblock_pattern = &sharpsl_bbt;
if (machine_is_akita() || machine_is_borzoi()) {
this->badblock_pattern = &sharpsl_akita_bbt;
this->autooob = &akita_oobinfo;
}
- this->enable_hwecc = sharpsl_nand_enable_hwecc;
- this->calculate_ecc = sharpsl_nand_calculate_ecc;
- this->correct_data = nand_correct_data;
+ this->ecc.hwctl = sharpsl_nand_enable_hwecc;
+ this->ecc.calculate = sharpsl_nand_calculate_ecc;
+ this->ecc.correct = nand_correct_data;
/* Scan to find existence of the device */
err = nand_scan(sharpsl_mtd, 1);
this->dev_ready = NULL;
/* 25 us command delay time */
this->chip_delay = 30;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Scan to find existance of the device */
if (nand_scan(toto_mtd, 1)) {
this->hwcontrol = ts7250_hwcontrol;
this->dev_ready = ts7250_device_ready;
this->chip_delay = 15;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
printk("Searching for NAND flash...\n");
/* Scan to find existence of the device */
/*
* Constants for ECC_MODES
*/
-
-/* No ECC. Usage is not recommended ! */
-#define NAND_ECC_NONE 0
-/* Software ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_SOFT 1
-/* Hardware ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_HW3_256 2
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW3_512 3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW6_512 4
-/* Hardware ECC 8 byte ECC per 512 Byte data */
-#define NAND_ECC_HW8_512 6
-/* Hardware ECC 12 byte ECC per 2048 Byte data */
-#define NAND_ECC_HW12_2048 7
+typedef enum {
+ NAND_ECC_NONE,
+ NAND_ECC_SOFT,
+ NAND_ECC_HW,
+ NAND_ECC_HW_SYNDROME,
+} nand_ecc_modes_t;
/*
* Constants for Hardware ECC
wait_queue_head_t wq;
};
+/**
+ * struct nand_ecc_ctrl - Control structure for ecc
+ * @mode: ecc mode
+ * @steps: number of ecc steps per page
+ * @size: data bytes per ecc step
+ * @bytes: ecc bytes per step
+ * @hwctl: function to control hardware ecc generator. Must only
+ * be provided if an hardware ECC is available
+ * @calculate: function for ecc calculation or readback from ecc hardware
+ * @correct: function for ecc correction, matching to ecc generator (sw/hw)
+ */
+struct nand_ecc_ctrl {
+ nand_ecc_modes_t mode;
+ int steps;
+ int size;
+ int bytes;
+ int (*hwctl)(struct mtd_info *mtd, int mode);
+ int (*calculate)(struct mtd_info *mtd,
+ const uint8_t *dat,
+ uint8_t *ecc_code);
+ int (*correct)(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc,
+ uint8_t *calc_ecc);
+};
+
/**
* struct nand_chip - NAND Private Flash Chip Data
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
- * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
- * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
- * be provided if a hardware ECC is available
+ * @ecc: [BOARDSPECIFIC] ecc control ctructure
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
- * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize: [INTERN] databytes used per ecc-calculation
- * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
- * @eccsteps: [INTERN] number of ecc calculation steps per page
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
* @state: [INTERN] the current state of the NAND device
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
- int (*calculate_ecc)(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code);
- int (*correct_data)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc);
- void (*enable_hwecc)(struct mtd_info *mtd, int mode);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
- int eccmode;
- int eccsize;
- int eccbytes;
- int eccsteps;
+ struct nand_ecc_ctrl ecc;
int chip_delay;
wait_queue_head_t wq;
nand_state_t state;
git.openpandora.org / pandora-kernel.git / commitdiff