drm/i915: don't enable plane, pipe and PLL prematurely

On Ironlake+ we need to enable these in a specific order.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 98967f3..9dcad31 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4222,9 +4222,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                        pipeconf &= ~PIPECONF_DOUBLE_WIDE;
        }
 
                        pipeconf &= ~PIPECONF_DOUBLE_WIDE;
        }
 

-       dspcntr |= DISPLAY_PLANE_ENABLE;
-       pipeconf |= PIPECONF_ENABLE;
-       dpll |= DPLL_VCO_ENABLE;
+       if (!HAS_PCH_SPLIT(dev)) {
+               dspcntr |= DISPLAY_PLANE_ENABLE;
+               pipeconf |= PIPECONF_ENABLE;
+               dpll |= DPLL_VCO_ENABLE;
+       }

 
        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
        drm_mode_debug_printmodeline(mode);
 
        DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
        drm_mode_debug_printmodeline(mode);