select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config MIPS_ATLAS
bool "MIPS Atlas board"
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This enables support for the MIPS Technologies Atlas evaluation
board.
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
bool
default y
+config GENERIC_HARDIRQS_NO__DO_IRQ
+ bool
+ default n
+
#
# Select some configuration options automatically based on user selections.
#
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config SWAP_IO_SPACE
bool
#include <asm/cpu.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
+#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/traps.h>
.mask = mask_ioasic_irq,
.mask_ack = ack_ioasic_irq,
.unmask = unmask_ioasic_irq,
- .end = end_ioasic_irq,
};
set_irq_chip_and_handler(i, &ioasic_irq_type,
handle_level_irq);
for (; i < base + IO_IRQ_LINES; i++)
- set_irq_chip_and_handler(i, &ioasic_dma_irq_type,
- handle_level_irq);
+ set_irq_chip(i, &ioasic_dma_irq_type);
ioasic_irq_base = base;
}
#include <linux/types.h>
#include <asm/inst.h>
+#include <asm/irq_regs.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
+#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/uaccess.h>
iob();
}
-static void end_kn02_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- unmask_kn02_irq(irq);
-}
-
static struct irq_chip kn02_irq_type = {
.typename = "KN02-CSR",
.ack = ack_kn02_irq,
.mask = mask_kn02_irq,
.mask_ack = ack_kn02_irq,
.unmask = unmask_kn02_irq,
- .end = end_kn02_irq,
};
ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
}
-static void emma2rh_irq_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
-}
-
struct irq_chip emma2rh_irq_controller = {
.typename = "emma2rh_irq",
.ack = emma2rh_irq_disable,
.mask = emma2rh_irq_disable,
.mask_ack = emma2rh_irq_disable,
.unmask = emma2rh_irq_enable,
- .end = emma2rh_irq_end,
};
void emma2rh_irq_init(u32 irq_base)
ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
}
-static void emma2rh_sw_irq_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
-}
-
struct irq_chip emma2rh_sw_irq_controller = {
.typename = "emma2rh_sw_irq",
.ack = emma2rh_sw_irq_disable,
.mask = emma2rh_sw_irq_disable,
.mask_ack = emma2rh_sw_irq_disable,
.unmask = emma2rh_sw_irq_enable,
- .end = emma2rh_sw_irq_end,
};
void emma2rh_sw_irq_init(u32 irq_base)
spin_unlock_irqrestore(&r4030_lock, flags);
}
-static void end_r4030_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_r4030_irq(irq);
-}
-
static struct irq_chip r4030_irq_type = {
.typename = "R4030",
.ack = disable_r4030_irq,
.mask = disable_r4030_irq,
.mask_ack = disable_r4030_irq,
.unmask = enable_r4030_irq,
- .end = end_r4030_irq,
};
void __init init_r4030_ints(void)
#include <asm/i8259.h>
#include <asm/io.h>
-void enable_8259A_irq(unsigned int irq);
-void disable_8259A_irq(unsigned int irq);
-
/*
* This is the 'legacy' 8259A Programmable Interrupt Controller,
* present in the majority of PC/AT boxes.
* moves to arch independent land
*/
+static int i8259A_auto_eoi;
DEFINE_SPINLOCK(i8259A_lock);
-
-static void end_8259A_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
- irq_desc[irq].action)
- enable_8259A_irq(irq);
-}
-
+/* some platforms call this... */
void mask_and_ack_8259A(unsigned int);
-static struct irq_chip i8259A_irq_type = {
- .typename = "XT-PIC",
- .enable = enable_8259A_irq,
- .disable = disable_8259A_irq,
- .ack = mask_and_ack_8259A,
- .end = end_8259A_irq,
+static struct irq_chip i8259A_chip = {
+ .name = "XT-PIC",
+ .mask = disable_8259A_irq,
+ .unmask = enable_8259A_irq,
+ .mask_ack = mask_and_ack_8259A,
};
/*
*/
static unsigned int cached_irq_mask = 0xffff;
-#define cached_21 (cached_irq_mask)
-#define cached_A1 (cached_irq_mask >> 8)
+#define cached_master_mask (cached_irq_mask)
+#define cached_slave_mask (cached_irq_mask >> 8)
void disable_8259A_irq(unsigned int irq)
{
spin_lock_irqsave(&i8259A_lock, flags);
cached_irq_mask |= mask;
if (irq & 8)
- outb(cached_A1,0xA1);
+ outb(cached_slave_mask, PIC_SLAVE_IMR);
else
- outb(cached_21,0x21);
+ outb(cached_master_mask, PIC_MASTER_IMR);
spin_unlock_irqrestore(&i8259A_lock, flags);
}
spin_lock_irqsave(&i8259A_lock, flags);
cached_irq_mask &= mask;
if (irq & 8)
- outb(cached_A1,0xA1);
+ outb(cached_slave_mask, PIC_SLAVE_IMR);
else
- outb(cached_21,0x21);
+ outb(cached_master_mask, PIC_MASTER_IMR);
spin_unlock_irqrestore(&i8259A_lock, flags);
}
spin_lock_irqsave(&i8259A_lock, flags);
if (irq < 8)
- ret = inb(0x20) & mask;
+ ret = inb(PIC_MASTER_CMD) & mask;
else
- ret = inb(0xA0) & (mask >> 8);
+ ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
spin_unlock_irqrestore(&i8259A_lock, flags);
return ret;
void make_8259A_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- set_irq_chip(irq, &i8259A_irq_type);
+ set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
enable_irq(irq);
}
int irqmask = 1 << irq;
if (irq < 8) {
- outb(0x0B,0x20); /* ISR register */
- value = inb(0x20) & irqmask;
- outb(0x0A,0x20); /* back to the IRR register */
+ outb(0x0B,PIC_MASTER_CMD); /* ISR register */
+ value = inb(PIC_MASTER_CMD) & irqmask;
+ outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
return value;
}
- outb(0x0B,0xA0); /* ISR register */
- value = inb(0xA0) & (irqmask >> 8);
- outb(0x0A,0xA0); /* back to the IRR register */
+ outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
+ value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
+ outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
return value;
}
spin_lock_irqsave(&i8259A_lock, flags);
/*
- * Lightweight spurious IRQ detection. We do not want to overdo
- * spurious IRQ handling - it's usually a sign of hardware problems, so
- * we only do the checks we can do without slowing down good hardware
- * nnecesserily.
+ * Lightweight spurious IRQ detection. We do not want
+ * to overdo spurious IRQ handling - it's usually a sign
+ * of hardware problems, so we only do the checks we can
+ * do without slowing down good hardware unnecessarily.
*
- * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting
- * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A.
- * Thus we can check spurious 8259A IRQs without doing the quite slow
- * i8259A_irq_real() call for every IRQ. This does not cover 100% of
- * spurious interrupts, but should be enough to warn the user that
- * there is something bad going on ...
+ * Note that IRQ7 and IRQ15 (the two spurious IRQs
+ * usually resulting from the 8259A-1|2 PICs) occur
+ * even if the IRQ is masked in the 8259A. Thus we
+ * can check spurious 8259A IRQs without doing the
+ * quite slow i8259A_irq_real() call for every IRQ.
+ * This does not cover 100% of spurious interrupts,
+ * but should be enough to warn the user that there
+ * is something bad going on ...
*/
if (cached_irq_mask & irqmask)
goto spurious_8259A_irq;
handle_real_irq:
if (irq & 8) {
- inb(0xA1); /* DUMMY - (do we need this?) */
- outb(cached_A1,0xA1);
- outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
- outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
+ inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
+ outb(cached_slave_mask, PIC_SLAVE_IMR);
+ outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
+ outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
} else {
- inb(0x21); /* DUMMY - (do we need this?) */
- outb(cached_21,0x21);
- outb(0x60+irq,0x20); /* 'Specific EOI' to master */
+ inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
+ outb(cached_master_mask, PIC_MASTER_IMR);
+ outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
}
#ifdef CONFIG_MIPS_MT_SMTC
if (irq_hwmask[irq] & ST0_IM)
goto handle_real_irq;
{
- static int spurious_irq_mask = 0;
+ static int spurious_irq_mask;
/*
* At this point we can be sure the IRQ is spurious,
* lets ACK and report it. [once per IRQ]
static int i8259A_resume(struct sys_device *dev)
{
- init_8259A(0);
+ init_8259A(i8259A_auto_eoi);
+ return 0;
+}
+
+static int i8259A_shutdown(struct sys_device *dev)
+{
+ /* Put the i8259A into a quiescent state that
+ * the kernel initialization code can get it
+ * out of.
+ */
+ outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
+ outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
return 0;
}
static struct sysdev_class i8259_sysdev_class = {
set_kset_name("i8259"),
.resume = i8259A_resume,
+ .shutdown = i8259A_shutdown,
};
static struct sys_device device_i8259A = {
{
unsigned long flags;
+ i8259A_auto_eoi = auto_eoi;
+
spin_lock_irqsave(&i8259A_lock, flags);
- outb(0xff, 0x21); /* mask all of 8259A-1 */
- outb(0xff, 0xA1); /* mask all of 8259A-2 */
+ outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
+ outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
/*
* outb_p - this has to work on a wide range of PC hardware.
*/
- outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
- outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */
- outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
- if (auto_eoi)
- outb_p(0x03, 0x21); /* master does Auto EOI */
- else
- outb_p(0x01, 0x21); /* master expects normal EOI */
-
- outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
- outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */
- outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
- outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
- is to be investigated) */
-
+ outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
+ outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
+ outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
+ if (auto_eoi) /* master does Auto EOI */
+ outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
+ else /* master expects normal EOI */
+ outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
+
+ outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
+ outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
+ outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
+ outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
if (auto_eoi)
/*
- * in AEOI mode we just have to mask the interrupt
+ * In AEOI mode we just have to mask the interrupt
* when acking.
*/
- i8259A_irq_type.ack = disable_8259A_irq;
+ i8259A_chip.mask_ack = disable_8259A_irq;
else
- i8259A_irq_type.ack = mask_and_ack_8259A;
+ i8259A_chip.mask_ack = mask_and_ack_8259A;
udelay(100); /* wait for 8259A to initialize */
- outb(cached_21, 0x21); /* restore master IRQ mask */
- outb(cached_A1, 0xA1); /* restore slave IRQ mask */
+ outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
+ outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
spin_unlock_irqrestore(&i8259A_lock, flags);
}
};
static struct resource pic1_io_resource = {
- .name = "pic1", .start = 0x20, .end = 0x21, .flags = IORESOURCE_BUSY
+ .name = "pic1",
+ .start = PIC_MASTER_CMD,
+ .end = PIC_MASTER_IMR,
+ .flags = IORESOURCE_BUSY
};
static struct resource pic2_io_resource = {
- .name = "pic2", .start = 0xa0, .end = 0xa1, .flags = IORESOURCE_BUSY
+ .name = "pic2",
+ .start = PIC_SLAVE_CMD,
+ .end = PIC_SLAVE_IMR,
+ .flags = IORESOURCE_BUSY
};
/*
init_8259A(0);
for (i = 0; i < 16; i++)
- set_irq_chip(i, &i8259A_irq_type);
+ set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
- setup_irq(2, &irq2);
+ setup_irq(PIC_CASCADE_IR, &irq2);
}
}
}
-/*
- * End IRQ processing
- */
-static void end_mv64340_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- unmask_mv64340_irq(irq);
-}
-
/*
* Interrupt handler for interrupts coming from the Marvell chip.
* It could be built in ethernet ports etc...
.mask = mask_mv64340_irq,
.mask_ack = mask_mv64340_irq,
.unmask = unmask_mv64340_irq,
- .end = end_mv64340_irq,
};
void __init mv64340_irq_init(unsigned int base)
clear_c0_intcontrol(0x100 << (irq - irq_base));
}
-static void rm7k_cpu_irq_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- unmask_rm7k_irq(irq);
-}
-
static struct irq_chip rm7k_irq_controller = {
.typename = "RM7000",
.ack = mask_rm7k_irq,
.mask = mask_rm7k_irq,
.mask_ack = mask_rm7k_irq,
.unmask = unmask_rm7k_irq,
- .end = rm7k_cpu_irq_end,
};
void __init rm7k_cpu_irq_init(int base)
on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
}
-static void rm9k_cpu_irq_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- unmask_rm9k_irq(irq);
-}
-
static struct irq_chip rm9k_irq_controller = {
.typename = "RM9000",
.ack = mask_rm9k_irq,
.mask = mask_rm9k_irq,
.mask_ack = mask_rm9k_irq,
.unmask = unmask_rm9k_irq,
- .end = rm9k_cpu_irq_end,
};
static struct irq_chip rm9k_perfcounter_irq = {
.mask = mask_rm9k_irq,
.mask_ack = mask_rm9k_irq,
.unmask = unmask_rm9k_irq,
- .end = rm9k_cpu_irq_end,
};
unsigned int rm9000_perfcount_irq;
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
- seq_printf(p, " %14s", irq_desc[i].chip->typename);
+ seq_printf(p, " %14s", irq_desc[i].chip->name);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
irq_disable_hazard();
}
-static void mips_cpu_irq_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- unmask_mips_irq(irq);
-}
-
static struct irq_chip mips_cpu_irq_controller = {
.typename = "MIPS",
.ack = mask_mips_irq,
.mask_ack = mask_mips_irq,
.unmask = unmask_mips_irq,
.eoi = unmask_mips_irq,
- .end = mips_cpu_irq_end,
};
/*
mask_mips_mt_irq(irq);
}
-#define mips_mt_cpu_irq_end mips_cpu_irq_end
-
static struct irq_chip mips_mt_cpu_irq_controller = {
.typename = "MIPS",
.startup = mips_mt_cpu_irq_startup,
.mask_ack = mips_mt_cpu_irq_ack,
.unmask = unmask_mips_mt_irq,
.eoi = unmask_mips_mt_irq,
- .end = mips_mt_cpu_irq_end,
};
void __init mips_cpu_irq_init(int irq_base)
*lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
}
-static void end_lasat_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_lasat_irq(irq);
-}
-
static struct irq_chip lasat_irq_type = {
.typename = "Lasat",
.ack = disable_lasat_irq,
.mask = disable_lasat_irq,
.mask_ack = disable_lasat_irq,
.unmask = enable_lasat_irq,
- .end = end_lasat_irq,
};
static inline int ls1bit32(unsigned int x)
value = OCELOT_FPGA_READ(INTMASK);
}
-/*
- * End IRQ processing
- */
-static void end_cpci_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- unmask_cpci_irq(irq);
-}
-
/*
* Interrupt handler for interrupts coming from the FPGA chip.
* It could be built in ethernet ports etc...
.mask = mask_cpci_irq,
.mask_ack = mask_cpci_irq,
.unmask = unmask_cpci_irq,
- .end = end_cpci_irq,
};
void cpci_irq_init(void)
value = OCELOT_FPGA_READ(UART_INTMASK);
}
-/*
- * End IRQ processing
- */
-static void end_uart_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- unmask_uart_irq(irq);
-}
-
/*
* Interrupt handler for interrupts coming from the FPGA chip.
*/
.mask = mask_uart_irq,
.mask_ack = mask_uart_irq,
.unmask = unmask_uart_irq,
- .end = end_uart_irq,
};
void uart_irq_init(void)
return prev_priority;
}
-static void end_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
- unmask_irq(irq);
- }
-}
-
static struct irq_chip level_irq_type = {
.typename = "PNX Level IRQ",
.ack = mask_irq,
.mask = mask_irq,
.mask_ack = mask_irq,
.unmask = unmask_irq,
- .end = end_irq,
};
static struct irqaction gic_action = {
sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
}
-static void end_local0_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_local0_irq(irq);
-}
-
static struct irq_chip ip22_local0_irq_type = {
.typename = "IP22 local 0",
.ack = disable_local0_irq,
.mask = disable_local0_irq,
.mask_ack = disable_local0_irq,
.unmask = enable_local0_irq,
- .end = end_local0_irq,
};
static void enable_local1_irq(unsigned int irq)
sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
}
-static void end_local1_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_local1_irq(irq);
-}
-
static struct irq_chip ip22_local1_irq_type = {
.typename = "IP22 local 1",
.ack = disable_local1_irq,
.mask = disable_local1_irq,
.mask_ack = disable_local1_irq,
.unmask = enable_local1_irq,
- .end = end_local1_irq,
};
static void enable_local2_irq(unsigned int irq)
sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}
-static void end_local2_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_local2_irq(irq);
-}
-
static struct irq_chip ip22_local2_irq_type = {
.typename = "IP22 local 2",
.ack = disable_local2_irq,
.mask = disable_local2_irq,
.mask_ack = disable_local2_irq,
.unmask = enable_local2_irq,
- .end = end_local2_irq,
};
static void enable_local3_irq(unsigned int irq)
sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}
-static void end_local3_irq (unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_local3_irq(irq);
-}
-
static struct irq_chip ip22_local3_irq_type = {
.typename = "IP22 local 3",
.ack = disable_local3_irq,
.mask = disable_local3_irq,
.mask_ack = disable_local3_irq,
.unmask = enable_local3_irq,
- .end = end_local3_irq,
};
static void indy_local0_irqdispatch(void)
intr_disconnect_level(cpu, swlevel);
}
-static void end_bridge_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
- irq_desc[irq].action)
- enable_bridge_irq(irq);
-}
-
static struct irq_chip bridge_irq_type = {
.typename = "bridge",
.startup = startup_bridge_irq,
.mask = disable_bridge_irq,
.mask_ack = disable_bridge_irq,
.unmask = enable_bridge_irq,
- .end = end_bridge_irq,
};
void __devinit register_bridge_irq(unsigned int irq)
{
}
-static void end_rt_irq(unsigned int irq)
-{
-}
-
static struct irq_chip rt_irq_type = {
.typename = "SN HUB RT timer",
.ack = disable_rt_irq,
.mask_ack = disable_rt_irq,
.unmask = enable_rt_irq,
.eoi = enable_rt_irq,
- .end = end_rt_irq,
};
static struct irqaction rt_irqaction = {
#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
-#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
-#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
#define TX4927_IRQ_ALL 0xffffffff
#endif
| TX4927_IRQ_WARN | TX4927_IRQ_EROR
// | TX4927_IRQ_CP0_INIT
// | TX4927_IRQ_CP0_ENABLE
-// | TX4927_IRQ_CP0_DISABLE
// | TX4927_IRQ_CP0_ENDIRQ
// | TX4927_IRQ_PIC_INIT
// | TX4927_IRQ_PIC_ENABLE
// | TX4927_IRQ_PIC_DISABLE
-// | TX4927_IRQ_PIC_ENDIRQ
// | TX4927_IRQ_INIT
// | TX4927_IRQ_NEST1
// | TX4927_IRQ_NEST2
static void tx4927_irq_cp0_enable(unsigned int irq);
static void tx4927_irq_cp0_disable(unsigned int irq);
-static void tx4927_irq_cp0_end(unsigned int irq);
static void tx4927_irq_pic_enable(unsigned int irq);
static void tx4927_irq_pic_disable(unsigned int irq);
-static void tx4927_irq_pic_end(unsigned int irq);
/*
* Kernel structs for all pic's
.mask = tx4927_irq_cp0_disable,
.mask_ack = tx4927_irq_cp0_disable,
.unmask = tx4927_irq_cp0_enable,
- .end = tx4927_irq_cp0_end,
};
#define TX4927_PIC_NAME "TX4927-PIC"
.mask = tx4927_irq_pic_disable,
.mask_ack = tx4927_irq_pic_disable,
.unmask = tx4927_irq_pic_enable,
- .end = tx4927_irq_pic_end,
};
#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
}
-static void tx4927_irq_cp0_end(unsigned int irq)
-{
- TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
-
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- tx4927_irq_cp0_enable(irq);
- }
-}
-
/*
* Functions for pic
*/
tx4927_irq_pic_mask(irq), 0);
}
-static void tx4927_irq_pic_end(unsigned int irq)
-{
- TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
-
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- tx4927_irq_pic_enable(irq);
- }
-}
-
/*
* Main init functions
*/
#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
-#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
-// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
-static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
.mask = toshiba_rbtx4927_irq_ioc_disable,
.mask_ack = toshiba_rbtx4927_irq_ioc_disable,
.unmask = toshiba_rbtx4927_irq_ioc_enable,
- .end = toshiba_rbtx4927_irq_ioc_end,
};
#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
}
-static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
-{
- TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
- "irq=%d\n", irq);
-
- if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
- || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
- TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
- "bad irq=%d\n", irq);
- panic("\n");
- }
-
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- toshiba_rbtx4927_irq_ioc_enable(irq);
- }
-}
-
/**********************************************************************************/
/* Functions for isa */
static void tx4938_irq_cp0_enable(unsigned int irq);
static void tx4938_irq_cp0_disable(unsigned int irq);
-static void tx4938_irq_cp0_end(unsigned int irq);
static void tx4938_irq_pic_enable(unsigned int irq);
static void tx4938_irq_pic_disable(unsigned int irq);
-static void tx4938_irq_pic_end(unsigned int irq);
/**********************************************************************************/
/* Kernel structs for all pic's */
.mask = tx4938_irq_cp0_disable,
.mask_ack = tx4938_irq_cp0_disable,
.unmask = tx4938_irq_cp0_enable,
- .end = tx4938_irq_cp0_end,
};
#define TX4938_PIC_NAME "TX4938-PIC"
.mask = tx4938_irq_pic_disable,
.mask_ack = tx4938_irq_pic_disable,
.unmask = tx4938_irq_pic_enable,
- .end = tx4938_irq_pic_end,
};
static struct irqaction tx4938_irq_pic_action = {
clear_c0_status(tx4938_irq_cp0_mask(irq));
}
-static void
-tx4938_irq_cp0_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- tx4938_irq_cp0_enable(irq);
- }
-}
-
/**********************************************************************************/
/* Functions for pic */
/**********************************************************************************/
tx4938_irq_pic_mask(irq), 0);
}
-static void
-tx4938_irq_pic_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- tx4938_irq_pic_enable(irq);
- }
-}
-
/**********************************************************************************/
/* Main init functions */
/**********************************************************************************/
static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
-static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
.mask = toshiba_rbtx4938_irq_ioc_disable,
.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
.unmask = toshiba_rbtx4938_irq_ioc_enable,
- .end = toshiba_rbtx4938_irq_ioc_end,
};
#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
}
-static void
-toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
- toshiba_rbtx4938_irq_ioc_enable(irq);
- }
-}
-
extern void __init txx9_spi_irqinit(int irc_irq);
void __init arch_init_irq(void)
select ISA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config IBM_WORKPAD
bool "Support for IBM WorkPad z50"
select ISA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config NEC_CMBVR4133
bool "Support for NEC CMB-VR4133"
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
The TANBAC VR4131 multichip module(TB0225) and
the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config ZAO_CAPCELLA
bool "Support for ZAO Networks Capcella"
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config PCI_VR41XX
bool "Add PCI control unit support of NEC VR4100 series"
icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
}
-static void end_sysint1_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
-}
-
static struct irq_chip sysint1_irq_type = {
.typename = "SYSINT1",
.ack = disable_sysint1_irq,
.mask = disable_sysint1_irq,
.mask_ack = disable_sysint1_irq,
.unmask = enable_sysint1_irq,
- .end = end_sysint1_irq,
};
static void disable_sysint2_irq(unsigned int irq)
icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
}
-static void end_sysint2_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
-}
-
static struct irq_chip sysint2_irq_type = {
.typename = "SYSINT2",
.ack = disable_sysint2_irq,
.mask = disable_sysint2_irq,
.mask_ack = disable_sysint2_irq,
.unmask = enable_sysint2_irq,
- .end = end_sysint2_irq,
};
static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
#include <asm/io.h>
+/* i8259A PIC registers */
+#define PIC_MASTER_CMD 0x20
+#define PIC_MASTER_IMR 0x21
+#define PIC_MASTER_ISR PIC_MASTER_CMD
+#define PIC_MASTER_POLL PIC_MASTER_ISR
+#define PIC_MASTER_OCW3 PIC_MASTER_ISR
+#define PIC_SLAVE_CMD 0xa0
+#define PIC_SLAVE_IMR 0xa1
+
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR 2
+#define MASTER_ICW4_DEFAULT 0x01
+#define SLAVE_ICW4_DEFAULT 0x01
+#define PIC_ICW4_AEOI 2
+
extern spinlock_t i8259A_lock;
+extern void init_8259A(int auto_eoi);
+extern void enable_8259A_irq(unsigned int irq);
+extern void disable_8259A_irq(unsigned int irq);
+
extern void init_i8259_irqs(void);
+#define I8259A_IRQ_BASE 0
+
/*
* Do the traditional i8259 interrupt polling thing. This is for the few
* cases where no better interrupt acknowledge method is available and we
spin_lock(&i8259A_lock);
/* Perform an interrupt acknowledge cycle on controller 1. */
- outb(0x0C, 0x20); /* prepare for poll */
- irq = inb(0x20) & 7;
- if (irq == 2) {
+ outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
+ irq = inb(PIC_MASTER_CMD) & 7;
+ if (irq == PIC_CASCADE_IR) {
/*
* Interrupt is cascaded so perform interrupt
* acknowledge on controller 2.
*/
- outb(0x0C, 0xA0); /* prepare for poll */
- irq = (inb(0xA0) & 7) + 8;
+ outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
+ irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
}
if (unlikely(irq == 7)) {
* significant bit is not set then there is no valid
* interrupt.
*/
- outb(0x0B, 0x20); /* ISR register */
- if(~inb(0x20) & 0x80)
+ outb(0x0B, PIC_MASTER_ISR); /* ISR register */
+ if(~inb(PIC_MASTER_ISR) & 0x80)
irq = -1;
}
spin_unlock(&i8259A_lock);
- return irq;
+ return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
}
#endif /* _ASM_I8259_H */
#define __pte_offset(address) \
(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address) \
- ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+#define pte_offset_kernel(dir, address) \
+ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_map(dir, address) \
((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define __pte_offset(address) \
(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address) \
- ((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
+ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
#define pte_offset_map(dir, address) \
((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_offset_map_nested(dir, address) \
git.openpandora.org / pandora-kernel.git / commitdiff