[ARM] 4135/1: Add support for the L210/L220 cache controllers

This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index a84eed9..af3fa9d 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -612,3 +612,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 config OUTER_CACHE
        bool
        default n
+
+config CACHE_L2X0
+       bool
+       select OUTER_CACHE

diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index d2f5672..2f8b959 100644 (file)
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -66,3 +66,5 @@ obj-$(CONFIG_CPU_SA1100)      += proc-sa1100.o
 obj-$(CONFIG_CPU_XSCALE)       += proc-xscale.o
 obj-$(CONFIG_CPU_XSC3)         += proc-xsc3.o
 obj-$(CONFIG_CPU_V6)           += proc-v6.o
+
+obj-$(CONFIG_CACHE_L2X0)       += cache-l2x0.o

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
new file mode 100644 (file)
index 0000000..08a36f1
--- /dev/null
+++ b/arch/arm/mm/cache-l2x0.c
@@ -0,0 +1,104 @@
+/*
+ * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define CACHE_LINE_SIZE                32
+
+static void __iomem *l2x0_base;
+
+static inline void sync_writel(unsigned long val, unsigned long reg,
+                              unsigned long complete_mask)
+{
+       writel(val, l2x0_base + reg);
+       /* wait for the operation to complete */
+       while (readl(l2x0_base + reg) & complete_mask)
+               ;
+}
+
+static inline void cache_sync(void)
+{
+       sync_writel(0, L2X0_CACHE_SYNC, 1);
+}
+
+static inline void l2x0_inv_all(void)
+{
+       /* invalidate all ways */
+       sync_writel(0xff, L2X0_INV_WAY, 0xff);
+       cache_sync();
+}
+
+static void l2x0_inv_range(unsigned long start, unsigned long end)
+{
+       unsigned long addr;
+
+       start &= ~(CACHE_LINE_SIZE - 1);
+       for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+               sync_writel(addr, L2X0_INV_LINE_PA, 1);
+       cache_sync();
+}
+
+static void l2x0_clean_range(unsigned long start, unsigned long end)
+{
+       unsigned long addr;
+
+       start &= ~(CACHE_LINE_SIZE - 1);
+       for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+               sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
+       cache_sync();
+}
+
+static void l2x0_flush_range(unsigned long start, unsigned long end)
+{
+       unsigned long addr;
+
+       start &= ~(CACHE_LINE_SIZE - 1);
+       for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
+               sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
+       cache_sync();
+}
+
+void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+{
+       __u32 aux;
+
+       l2x0_base = base;
+
+       /* disable L2X0 */
+       writel(0, l2x0_base + L2X0_CTRL);
+
+       aux = readl(l2x0_base + L2X0_AUX_CTRL);
+       aux &= aux_mask;
+       aux |= aux_val;
+       writel(aux, l2x0_base + L2X0_AUX_CTRL);
+
+       l2x0_inv_all();
+
+       /* enable L2X0 */
+       writel(1, l2x0_base + L2X0_CTRL);
+
+       outer_cache.inv_range = l2x0_inv_range;
+       outer_cache.clean_range = l2x0_clean_range;
+       outer_cache.flush_range = l2x0_flush_range;
+
+       printk(KERN_INFO "L2X0 cache controller enabled\n");
+}

diff --git a/include/asm-arm/hardware/cache-l2x0.h b/include/asm-arm/hardware/cache-l2x0.h
new file mode 100644 (file)
index 0000000..54029a7
--- /dev/null
+++ b/include/asm-arm/hardware/cache-l2x0.h
@@ -0,0 +1,56 @@
+/*
+ * include/asm-arm/hardware/cache-l2x0.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_HARDWARE_L2X0_H
+#define __ASM_ARM_HARDWARE_L2X0_H
+
+#define L2X0_CACHE_ID                  0x000
+#define L2X0_CACHE_TYPE                        0x004
+#define L2X0_CTRL                      0x100
+#define L2X0_AUX_CTRL                  0x104
+#define L2X0_EVENT_CNT_CTRL            0x200
+#define L2X0_EVENT_CNT1_CFG            0x204
+#define L2X0_EVENT_CNT0_CFG            0x208
+#define L2X0_EVENT_CNT1_VAL            0x20C
+#define L2X0_EVENT_CNT0_VAL            0x210
+#define L2X0_INTR_MASK                 0x214
+#define L2X0_MASKED_INTR_STAT          0x218
+#define L2X0_RAW_INTR_STAT             0x21C
+#define L2X0_INTR_CLEAR                        0x220
+#define L2X0_CACHE_SYNC                        0x730
+#define L2X0_INV_LINE_PA               0x770
+#define L2X0_INV_WAY                   0x77C
+#define L2X0_CLEAN_LINE_PA             0x7B0
+#define L2X0_CLEAN_LINE_IDX            0x7B8
+#define L2X0_CLEAN_WAY                 0x7BC
+#define L2X0_CLEAN_INV_LINE_PA         0x7F0
+#define L2X0_CLEAN_INV_LINE_IDX                0x7F8
+#define L2X0_CLEAN_INV_WAY             0x7FC
+#define L2X0_LOCKDOWN_WAY_D            0x900
+#define L2X0_LOCKDOWN_WAY_I            0x904
+#define L2X0_TEST_OPERATION            0xF00
+#define L2X0_LINE_DATA                 0xF10
+#define L2X0_LINE_TAG                  0xF30
+#define L2X0_DEBUG_CTRL                        0xF40
+
+#ifndef __ASSEMBLY__
+extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#endif
+
+#endif