drm/i915: support 3 pipes on IVB+

Well almost anyway.  IVB has 3 planes, pipes, transcoders, and FDI
interfaces, but only 2 pipe PLLs.  So two of the pipes must use the same
pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode
and one other, etc.).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d76da38..2eac955 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2035,7 +2035,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        spin_lock_init(&dev_priv->error_lock);
        spin_lock_init(&dev_priv->rps_lock);
 
-       if (IS_MOBILE(dev) || !IS_GEN2(dev))
+       if (IS_IVYBRIDGE(dev))
+               dev_priv->num_pipe = 3;
+       else if (IS_MOBILE(dev) || !IS_GEN2(dev))
                dev_priv->num_pipe = 2;
        else
                dev_priv->num_pipe = 1;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c02cdac..c5ca0d3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -674,8 +674,8 @@ typedef struct drm_i915_private {
        /* Panel fitter placement and size for Ironlake+ */
        u32 pch_pf_pos, pch_pf_size;
 
-       struct drm_crtc *plane_to_crtc_mapping[2];
-       struct drm_crtc *pipe_to_crtc_mapping[2];
+       struct drm_crtc *plane_to_crtc_mapping[3];
+       struct drm_crtc *pipe_to_crtc_mapping[3];
        wait_queue_head_t pending_flip_queue;
        bool flip_pending_is_done;
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dade95c..6b1a1ed 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2092,6 +2092,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
        switch (plane) {
        case 0:
        case 1:
+       case 2:
                break;
        default:
                DRM_ERROR("Can't update plane %d in SAREA\n", plane);
@@ -2191,6 +2192,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
        case 0:
        case 1:
                break;
+       case 2:
+               if (IS_IVYBRIDGE(dev))
+                       break;
+               /* fall through otherwise */
        default:
                DRM_ERROR("no plane for crtc\n");
                return -EINVAL;
@@ -2889,6 +2894,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
                        temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
                else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
                        temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+               else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
+                       temp |= (TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
                I915_WRITE(PCH_DPLL_SEL, temp);
        }
 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3d73374..3009d2a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2215,7 +2215,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
                                  ironlake_panel_vdd_work);
        }
 
-       intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+       intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
        connector->interlace_allowed = true;
        connector->doublescan_allowed = 0;
 

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 75026ba..185c5aa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -514,7 +514,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
        connector->polled = DRM_CONNECTOR_POLL_HPD;
        connector->interlace_allowed = 0;
        connector->doublescan_allowed = 0;
-       intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+       intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
        /* Set up the DDC bus. */
        if (sdvox_reg == SDVOB) {

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 31da77f..42f165a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -888,9 +888,11 @@ bool intel_lvds_init(struct drm_device *dev)
        intel_encoder->type = INTEL_OUTPUT_LVDS;
 
        intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
-       intel_encoder->crtc_mask = (1 << 1);
-       if (INTEL_INFO(dev)->gen >= 5)
-               intel_encoder->crtc_mask |= (1 << 0);
+       if (HAS_PCH_SPLIT(dev))
+               intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+       else
+               intel_encoder->crtc_mask = (1 << 1);
+
        drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
        drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
        connector->display_info.subpixel_order = SubPixelHorizontalRGB;

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 1b97d1f..6db3b1c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2203,7 +2203,7 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
                              bytes[0], bytes[1]);
                return false;
        }
-       intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
+       intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
        return true;
 }