MXC arch: Simplify architecture's irq sources

Simplify architecture's irq headers and sources, to share these files
between MXC3 and MXC2.

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>

diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 88f0cfa..1fbe01d 100644 (file)
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
 /*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
  */
 
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <asm/hardware.h>
+#include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
+#define AVIC_BASE              IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL           (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK            (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM          (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM         (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH                (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL                (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH          (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL          (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7       (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6       (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5       (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4       (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3       (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2       (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1       (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0       (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR           (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR           (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH           (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL           (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH           (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL           (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH            (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL            (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH            (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL            (AVIC_BASE + 0x64)      /* fast int pending low */
+
+#define SYSTEM_PREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH                3
+#define IIM_PROD_REV_LEN       5
+
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
 }
 
 static struct irq_chip mxc_avic_chip = {
-       .mask_ack = mxc_mask_irq,
+       .ack = mxc_mask_irq,
        .mask = mxc_mask_irq,
        .unmask = mxc_unmask_irq,
 };

diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205..f416130 100644 (file)
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
 
 #include <asm/hardware.h>
 
-#define MXC_IRQ_TO_EXPIO(irq)  ((irq) - MXC_EXP_IO_BASE)
-
-#define MXC_IRQ_TO_GPIO(irq)   ((irq) - MXC_GPIO_INT_BASE)
-#define MXC_GPIO_TO_IRQ(x)     (MXC_GPIO_INT_BASE + x)
-
-/* Number of normal interrupts */
-#define NR_IRQS                (MXC_MAX_INT_LINES + \
-                       MXC_MAX_GPIO_LINES + \
-                       MXC_MAX_VIRTUAL_INTS)
-
-/* Number of fast interrupts */
-#define NR_FIQS                MXC_MAX_INTS
-
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */

diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 98e6a4c..a7373e4 100644 (file)
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
 #define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
 #define MXC_MAX_VIRTUAL_INTS   16
 
+#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
+
 /*!
  * Number of GPIO port as defined in the IC Spec
  */

diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 1df4e2f..3e1c4de 100644 (file)
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -29,42 +29,4 @@
 # define cpu_is_mx31() (0)
 #endif
 
-/*
- *****************************************
- * AVIC Registers                        *
- *****************************************
- */
-#define AVIC_BASE              IO_ADDRESS(AVIC_BASE_ADDR)
-#define AVIC_INTCNTL           (AVIC_BASE + 0x00)      /* int control reg */
-#define AVIC_NIMASK            (AVIC_BASE + 0x04)      /* int mask reg */
-#define AVIC_INTENNUM          (AVIC_BASE + 0x08)      /* int enable number reg */
-#define AVIC_INTDISNUM         (AVIC_BASE + 0x0C)      /* int disable number reg */
-#define AVIC_INTENABLEH                (AVIC_BASE + 0x10)      /* int enable reg high */
-#define AVIC_INTENABLEL                (AVIC_BASE + 0x14)      /* int enable reg low */
-#define AVIC_INTTYPEH          (AVIC_BASE + 0x18)      /* int type reg high */
-#define AVIC_INTTYPEL          (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7       (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6       (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5       (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4       (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3       (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2       (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1       (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0       (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
-#define AVIC_NIVECSR           (AVIC_BASE + 0x40)      /* norm int vector/status */
-#define AVIC_FIVECSR           (AVIC_BASE + 0x44)      /* fast int vector/status */
-#define AVIC_INTSRCH           (AVIC_BASE + 0x48)      /* int source reg high */
-#define AVIC_INTSRCL           (AVIC_BASE + 0x4C)      /* int source reg low */
-#define AVIC_INTFRCH           (AVIC_BASE + 0x50)      /* int force reg high */
-#define AVIC_INTFRCL           (AVIC_BASE + 0x54)      /* int force reg low */
-#define AVIC_NIPNDH            (AVIC_BASE + 0x58)      /* norm int pending high */
-#define AVIC_NIPNDL            (AVIC_BASE + 0x5C)      /* norm int pending low */
-#define AVIC_FIPNDH            (AVIC_BASE + 0x60)      /* fast int pending high */
-#define AVIC_FIPNDL            (AVIC_BASE + 0x64)      /* fast int pending low */
-
-#define SYSTEM_PREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH                3
-#define IIM_PROD_REV_LEN       5
-
 #endif /*  __ASM_ARCH_MXC_H__ */