drm/i915: Add register whitelist for DRM master

These are used to implement scanline waits in the X server.

v2: Use #defines instead of magic numbers

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 7249b51..0182c7c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -281,6 +281,19 @@ static const u32 gen7_blt_regs[] = {
        BCS_SWCTRL,
 };
 
+static const u32 ivb_master_regs[] = {
+       FORCEWAKE_MT,
+       DERRMR,
+       GEN7_PIPE_DE_LOAD_SL(PIPE_A),
+       GEN7_PIPE_DE_LOAD_SL(PIPE_B),
+       GEN7_PIPE_DE_LOAD_SL(PIPE_C),
+};
+
+static const u32 hsw_master_regs[] = {
+       FORCEWAKE_MT,
+       DERRMR,
+};
+
 #undef REG64
 
 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
@@ -409,6 +422,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
                ring->reg_table = gen7_render_regs;
                ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 
+               if (IS_HASWELL(ring->dev)) {
+                       ring->master_reg_table = hsw_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+               } else {
+                       ring->master_reg_table = ivb_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+               }
+
                ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
                break;
        case VCS:
@@ -428,6 +449,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
                ring->reg_table = gen7_blt_regs;
                ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 
+               if (IS_HASWELL(ring->dev)) {
+                       ring->master_reg_table = hsw_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+               } else {
+                       ring->master_reg_table = ivb_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+               }
+
                ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
                break;
        case VECS:

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6247843..d90171b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -416,6 +416,12 @@
 /* There are the 4 64-bit counter registers, one for each stream output */
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
 
+#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
+#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
+#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
+                                        _GEN7_PIPEA_DE_LOAD_SL, \
+                                        _GEN7_PIPEB_DE_LOAD_SL)
+
 /*
  * Reset registers
  */