ARM: mx50: Add support to get the silicon revision
authorDinh Nguyen <Dinh.Nguyen@freescale.com>
Mon, 21 Mar 2011 21:30:35 +0000 (16:30 -0500)
committerSascha Hauer <s.hauer@pengutronix.de>
Wed, 23 Mar 2011 14:08:15 +0000 (15:08 +0100)
For MX50, the HW_ADADIG_DIGPROG register in the ANATOP module will
have the correct silicon revision:

Major       Minor   Description
0x50        0x0     TO1.0
0x50        0x1     TO1.1

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arch/arm/mach-mx5/cpu.c
arch/arm/plat-mxc/include/mach/mx50.h

index 3b4c307..472bdfa 100644 (file)
@@ -21,6 +21,7 @@
 static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG 0xB0
 
 static int get_mx51_srev(void)
 {
@@ -127,6 +128,44 @@ int mx53_revision(void)
 }
 EXPORT_SYMBOL(mx53_revision);
 
+static int get_mx50_srev(void)
+{
+       void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+       u32 rev;
+
+       if (!anatop) {
+               cpu_silicon_rev = -EINVAL;
+               return 0;
+       }
+
+       rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+       rev &= 0xff;
+
+       iounmap(anatop);
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_1_0;
+       else if (rev == 0x1)
+               return IMX_CHIP_REVISION_1_1;
+       return 0;
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+       if (!cpu_is_mx50())
+               return -EINVAL;
+
+       if (cpu_silicon_rev == -1)
+               cpu_silicon_rev = get_mx50_srev();
+
+       return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
 static int __init post_cpu_init(void)
 {
        unsigned int reg;
index aaec2a6..5f2da75 100644 (file)
 #define MX50_INT_APBHDMA_CHAN6 116
 #define MX50_INT_APBHDMA_CHAN7 117
 
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx50_revision(void);
+#endif
+
 #endif /* ifndef __MACH_MX50_H__ */