+ divider = 8;
+ if (snd_pcm_format_physical_width(params_format(params)) > 16)
+ divider = 4;
+
+ ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, divider);
+ if (ret < 0) {
+ pr_err(PREFIX "can't set SRG clock divider to %d\n", divider);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int omap3pandora_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ int ret;
+
+ /* Set McBSP clock back to internal for power saving to work */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK,
+ 0, SND_SOC_CLOCK_IN);