mm: Export migrate_page_move_mapping and migrate_page_copy

[pandora-kernel.git] / include / linux / pci_regs.h

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index be01380..411c412 100644 (file)
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -392,7 +392,7 @@
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6   /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7   /* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_RC_END   0x9     /* Root Complex Integrated Endpoint */
-#define  PCI_EXP_TYPE_RC_EC    0x10    /* Root Complex Event Collector */
+#define  PCI_EXP_TYPE_RC_EC    0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT     0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ      0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP         4       /* Device capabilities */
@@ -508,8 +508,18 @@
 #define PCI_EXP_RTSTA_PENDING  0x20000 /* PME pending */
 #define PCI_EXP_DEVCAP2                36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI   0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR   0x800   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MASK     0xc0000 /* OBFF support mechanism */
+#define  PCI_EXP_OBFF_MSG      0x40000 /* New message signaling */
+#define  PCI_EXP_OBFF_WAKE     0x80000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2                40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_ARI   0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_IDO_REQ_EN    0x100   /* ID-based ordering request enable */
+#define  PCI_EXP_IDO_CMP_EN    0x200   /* ID-based ordering completion enable */
+#define  PCI_EXP_LTR_EN                0x400   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MSGA_EN  0x2000  /* OBFF enable with Message type A */
+#define  PCI_EXP_OBFF_MSGB_EN  0x4000  /* OBFF enable with Message type B */
+#define  PCI_EXP_OBFF_WAKE_EN  0x6000  /* OBFF using WAKE# signaling */
 #define PCI_EXP_LNKCTL2                48      /* Link Control 2 */
 #define PCI_EXP_SLTCTL2                56      /* Slot Control 2 */
 
@@ -527,6 +537,7 @@
 #define PCI_EXT_CAP_ID_ARI     14
 #define PCI_EXT_CAP_ID_ATS     15
 #define PCI_EXT_CAP_ID_SRIOV   16
+#define PCI_EXT_CAP_ID_LTR     24
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS   4       /* Uncorrectable Error Status */
@@ -652,6 +663,26 @@
 #define  PCI_ATS_CTRL_STU(x)   ((x) & 0x1f)    /* Smallest Translation Unit */
 #define  PCI_ATS_MIN_STU       12      /* shift of minimum STU block */
 
+/* Page Request Interface */
+#define PCI_PRI_CAP            0x13    /* PRI capability ID */
+#define PCI_PRI_CONTROL_OFF    0x04    /* Offset of control register */
+#define PCI_PRI_STATUS_OFF     0x06    /* Offset of status register */
+#define PCI_PRI_ENABLE         0x0001  /* Enable mask */
+#define PCI_PRI_RESET          0x0002  /* Reset bit mask */
+#define PCI_PRI_STATUS_RF      0x0001  /* Request Failure */
+#define PCI_PRI_STATUS_UPRGI   0x0002  /* Unexpected PRG index */
+#define PCI_PRI_STATUS_STOPPED 0x0100  /* PRI Stopped */
+#define PCI_PRI_MAX_REQ_OFF    0x08    /* Cap offset for max reqs supported */
+#define PCI_PRI_ALLOC_REQ_OFF  0x0c    /* Cap offset for max reqs allowed */
+
+/* PASID capability */
+#define PCI_PASID_CAP          0x1b    /* PASID capability ID */
+#define PCI_PASID_CAP_OFF      0x04    /* PASID feature register */
+#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
+#define PCI_PASID_ENABLE       0x01    /* Enable/Supported bit */
+#define PCI_PASID_EXEC         0x02    /* Exec permissions Enable/Supported */
+#define PCI_PASID_PRIV         0x04    /* Priviledge Mode Enable/Support */
+
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP          0x04    /* SR-IOV Capabilities */
 #define  PCI_SRIOV_CAP_VFM     0x01    /* VF Migration Capable */
@@ -683,6 +714,12 @@
 #define  PCI_SRIOV_VFM_MO      0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV      0x3     /* Active.Available */
 
+#define PCI_LTR_MAX_SNOOP_LAT  0x4
+#define PCI_LTR_MAX_NOSNOOP_LAT        0x6
+#define  PCI_LTR_VALUE_MASK    0x000003ff
+#define  PCI_LTR_SCALE_MASK    0x00001c00
+#define  PCI_LTR_SCALE_SHIFT   10
+
 /* Access Control Service */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define  PCI_ACS_SV            0x01    /* Source Validation */