Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq

[pandora-kernel.git] / include / asm-powerpc / lppaca.h

diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
index c1bedab..821ea0c 100644 (file)
--- a/include/asm-powerpc/lppaca.h
+++ b/include/asm-powerpc/lppaca.h
@@ -18,6 +18,7 @@
  */
 #ifndef _ASM_POWERPC_LPPACA_H
 #define _ASM_POWERPC_LPPACA_H
+#ifdef __KERNEL__
 
 //=============================================================================
 //
@@ -26,8 +27,12 @@
 //
 //
 //----------------------------------------------------------------------------
+#include <linux/cache.h>
 #include <asm/types.h>
+#include <asm/mmu.h>
 
+/* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
+ * alignment is sufficient to prevent this */
 struct lppaca {
 //=============================================================================
 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
@@ -111,7 +116,7 @@ struct lppaca {
 
 
 //=============================================================================
-// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
+// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
 //=============================================================================
        // This is the yield_count.  An "odd" value (low bit on) means that
        // the processor is yielded (either because of an OS yield or a PLIC
@@ -123,9 +128,29 @@ struct lppaca {
        u8      reserved6[124];         // Reserved                     x04-x7F
 
 //=============================================================================
-// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
+// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
 //=============================================================================
        u8      pmc_save_area[256];     // PMC interrupt Area           x00-xFF
-};
+} __attribute__((__aligned__(0x400)));
 
+extern struct lppaca lppaca[];
+
+/*
+ * SLB shadow buffer structure as defined in the PAPR.  The save_area
+ * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
+ * ESID is stored in the lower 64bits, then the VSID.
+ */
+struct slb_shadow {
+       u32     persistent;             // Number of persistent SLBs    x00-x03
+       u32     buffer_length;          // Total shadow buffer length   x04-x07
+       u64     reserved;               // Alignment                    x08-x0f
+       struct  {
+               u64     esid;
+               u64     vsid;
+       } save_area[SLB_NUM_BOLTED];    //                              x10-x40
+} ____cacheline_aligned;
+
+extern struct slb_shadow slb_shadow[];
+
+#endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_LPPACA_H */