[PARISC] fix section mismatches in arch/parisc/kernel

[pandora-kernel.git] / include / asm-parisc / processor.h

diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index b73626f..6b294fb 100644 (file)
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -10,10 +10,9 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/threads.h>
-#include <linux/spinlock_types.h>
 
+#include <asm/prefetch.h>
 #include <asm/hardware.h>
-#include <asm/page.h>
 #include <asm/pdc.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
@@ -39,7 +38,7 @@
 #define DEFAULT_TASK_SIZE32    (0xFFF00000UL)
 #define DEFAULT_MAP_BASE32     (0x40000000UL)
 
-#ifdef __LP64__
+#ifdef CONFIG_64BIT
 #define DEFAULT_TASK_SIZE       (MAX_ADDRESS-0xf000000)
 #define DEFAULT_MAP_BASE        (0x200000000UL)
 #else
@@ -70,8 +69,8 @@ struct system_cpuinfo_parisc {
                char   sys_model_name[81]; /* PDC-ROM returnes this model name */
        } pdc;
 
-       char            *cpu_name;      /* e.g. "PA7300LC (PCX-L2)" */
-       char            *family_name;   /* e.g. "1.1e" */
+       const char      *cpu_name;      /* e.g. "PA7300LC (PCX-L2)" */
+       const char      *family_name;   /* e.g. "1.1e" */
 };
 
 
@@ -85,7 +84,6 @@ struct cpuinfo_parisc {
        unsigned long hpa;          /* Host Physical address */
        unsigned long txn_addr;     /* MMIO addr of EIR or id_eid */
 #ifdef CONFIG_SMP
-       spinlock_t lock;            /* synchronization for ipi's */
        unsigned long pending_ipi;  /* bitmap of type ipi_message_type */
        unsigned long ipi_count;    /* number ipi Interrupts */
 #endif
@@ -275,8 +273,8 @@ on downward growing arches, it looks like this:
  * it in here from the current->personality
  */
 
-#ifdef __LP64__
-#define USER_WIDE_MODE (personality(current->personality) == PER_LINUX)
+#ifdef CONFIG_64BIT
+#define USER_WIDE_MODE (!test_thread_flag(TIF_32BIT))
 #else
 #define USER_WIDE_MODE 0
 #endif
@@ -328,33 +326,20 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)  ((tsk)->thread.regs.iaoq[0])
 #define KSTK_ESP(tsk)  ((tsk)->thread.regs.gr[30])
 
+#define cpu_relax()    barrier()
 
-/*
- * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
- * In addition, many implementations do hardware prefetching of both
- * instructions and data.
- *
- * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
- * to gr0 but not in a way that Linux can use.  If the load would cause an
- * interruption (eg due to prefetching 0), it is suppressed on PA2.0
- * processors, but not on 7300LC.
- */
-#ifdef  CONFIG_PREFETCH
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-
-extern inline void prefetch(const void *addr)
-{
-       __asm__("ldw 0(%0), %%r0" : : "r" (addr));
-}
-
-extern inline void prefetchw(const void *addr)
+/* Used as a macro to identify the combined VIPT/PIPT cached
+ * CPUs which require a guarantee of coherency (no inequivalent
+ * aliases with different data, whether clean or not) to operate */
+static inline int parisc_requires_coherency(void)
 {
-       __asm__("ldd 0(%0), %%r0" : : "r" (addr));
-}
+#ifdef CONFIG_PA8X00
+       return (boot_cpu_data.cpu_type == mako) ||
+               (boot_cpu_data.cpu_type == mako2);
+#else
+       return 0;
 #endif
-
-#define cpu_relax()    barrier()
+}
 
 #endif /* __ASSEMBLY__ */