Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...

[pandora-kernel.git] / include / asm-arm / arch-s3c2410 / map.h

diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 27ba0ac..4505aef 100644 (file)
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -1,7 +1,7 @@
 /* linux/include/asm-arm/arch-s3c2410/map.h
  *
- * (c) 2003 Simtec Electronics
- *  Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2003 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
  *
  * S3C2410 - Memory map definitions
  *
@@ -25,7 +25,7 @@
  */
 
 #ifndef __ASSEMBLY__
-#define S3C2410_ADDR(x)          ((void __iomem *)0xF0000000 + (x))
+#define S3C2410_ADDR(x)          ((void __iomem __force *)0xF0000000 + (x))
 #else
 #define S3C2410_ADDR(x)          (0xF0000000 + (x))
 #endif
@@ -47,73 +47,65 @@
 #define S3C24XX_SZ_MEMCTRL SZ_1M
 
 /* USB host controller */
-#define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
 #define S3C2400_PA_USBHOST (0x14200000)
 #define S3C2410_PA_USBHOST (0x49000000)
 #define S3C24XX_SZ_USBHOST SZ_1M
 
 /* DMA controller */
-#define S3C24XX_VA_DMA    S3C2410_ADDR(0x00300000)
 #define S3C2400_PA_DMA    (0x14600000)
 #define S3C2410_PA_DMA    (0x4B000000)
 #define S3C24XX_SZ_DMA    SZ_1M
 
 /* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00400000)
+#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
 #define S3C2400_PA_CLKPWR  (0x14800000)
 #define S3C2410_PA_CLKPWR  (0x4C000000)
 #define S3C24XX_SZ_CLKPWR  SZ_1M
 
 /* LCD controller */
-#define S3C24XX_VA_LCD    S3C2410_ADDR(0x00600000)
+#define S3C24XX_VA_LCD    S3C2410_ADDR(0x00300000)
 #define S3C2400_PA_LCD    (0x14A00000)
 #define S3C2410_PA_LCD    (0x4D000000)
 #define S3C24XX_SZ_LCD    SZ_1M
 
 /* NAND flash controller */
-#define S3C24XX_VA_NAND           S3C2410_ADDR(0x00700000)
 #define S3C2410_PA_NAND           (0x4E000000)
 #define S3C24XX_SZ_NAND           SZ_1M
 
 /* MMC controller - available on the S3C2400 */
-#define S3C2400_VA_MMC            S3C2400_ADDR(0x00700000)
 #define S3C2400_PA_MMC            (0x15A00000)
 #define S3C2400_SZ_MMC            SZ_1M
 
 /* UARTs */
-#define S3C24XX_VA_UART           S3C2410_ADDR(0x00800000)
+#define S3C24XX_VA_UART           S3C2410_ADDR(0x00400000)
 #define S3C2400_PA_UART           (0x15000000)
 #define S3C2410_PA_UART           (0x50000000)
 #define S3C24XX_SZ_UART           SZ_1M
 
 /* Timers */
-#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00900000)
+#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
 #define S3C2400_PA_TIMER   (0x15100000)
 #define S3C2410_PA_TIMER   (0x51000000)
 #define S3C24XX_SZ_TIMER   SZ_1M
 
 /* USB Device port */
-#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00A00000)
+#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
 #define S3C2400_PA_USBDEV  (0x15200140)
 #define S3C2410_PA_USBDEV  (0x52000000)
 #define S3C24XX_SZ_USBDEV  SZ_1M
 
 /* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
+#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
 #define S3C2400_PA_WATCHDOG (0x15300000)
 #define S3C2410_PA_WATCHDOG (0x53000000)
 #define S3C24XX_SZ_WATCHDOG SZ_1M
 
 /* IIC hardware controller */
-#define S3C24XX_VA_IIC    S3C2410_ADDR(0x00C00000)
 #define S3C2400_PA_IIC    (0x15400000)
 #define S3C2410_PA_IIC    (0x54000000)
 #define S3C24XX_SZ_IIC    SZ_1M
 
-#define VA_IIC_BASE       (S3C24XX_VA_IIC)
-
 /* IIS controller */
-#define S3C24XX_VA_IIS    S3C2410_ADDR(0x00D00000)
 #define S3C2400_PA_IIS    (0x15508000)
 #define S3C2410_PA_IIS    (0x55000000)
 #define S3C24XX_SZ_IIS    SZ_1M
@@ -134,25 +126,21 @@
 #define S3C24XX_SZ_GPIO           SZ_1M
 
 /* RTC */
-#define S3C24XX_VA_RTC    S3C2410_ADDR(0x00F00000)
 #define S3C2400_PA_RTC    (0x15700040)
 #define S3C2410_PA_RTC    (0x57000000)
 #define S3C24XX_SZ_RTC    SZ_1M
 
 /* ADC */
-#define S3C24XX_VA_ADC    S3C2410_ADDR(0x01000000)
 #define S3C2400_PA_ADC    (0x15800000)
 #define S3C2410_PA_ADC    (0x58000000)
 #define S3C24XX_SZ_ADC    SZ_1M
 
 /* SPI */
-#define S3C24XX_VA_SPI    S3C2410_ADDR(0x01100000)
 #define S3C2400_PA_SPI    (0x15900000)
 #define S3C2410_PA_SPI    (0x59000000)
 #define S3C24XX_SZ_SPI    SZ_1M
 
 /* SDI */
-#define S3C24XX_VA_SDI    S3C2410_ADDR(0x01200000)
 #define S3C2410_PA_SDI    (0x5A000000)
 #define S3C24XX_SZ_SDI    SZ_1M
 
@@ -160,6 +148,11 @@
 #define S3C2440_PA_CAMIF   (0x4F000000)
 #define S3C2440_SZ_CAMIF   SZ_1M
 
+/* AC97 */
+
+#define S3C2440_PA_AC97           (0x5B000000)
+#define S3C2440_SZ_AC97           SZ_1M
+
 /* ISA style IO, for each machine to sort out mappings for, if it
  * implements it. We reserve two 16M regions for ISA.
  */