/* --------------------------------------------------------------------- */
-static void vgaHWSeqReset (struct savagefb_par *par, int start)
+static void vgaHWSeqReset(struct savagefb_par *par, int start)
{
if (start)
- VGAwSEQ (0x00, 0x01, par); /* Synchronous Reset */
+ VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
else
- VGAwSEQ (0x00, 0x03, par); /* End Reset */
+ VGAwSEQ(0x00, 0x03, par); /* End Reset */
}
-static void vgaHWProtect (struct savagefb_par *par, int on)
+static void vgaHWProtect(struct savagefb_par *par, int on)
{
unsigned char tmp;
/*
* Turn off screen and disable sequencer.
*/
- tmp = VGArSEQ (0x01, par);
+ tmp = VGArSEQ(0x01, par);
- vgaHWSeqReset (par, 1); /* start synchronous reset */
- VGAwSEQ (0x01, tmp | 0x20, par);/* disable the display */
+ vgaHWSeqReset(par, 1); /* start synchronous reset */
+ VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
VGAenablePalette(par);
} else {
* Reenable sequencer, then turn on screen.
*/
- tmp = VGArSEQ (0x01, par);
+ tmp = VGArSEQ(0x01, par);
- VGAwSEQ (0x01, tmp & ~0x20, par);/* reenable display */
- vgaHWSeqReset (par, 0); /* clear synchronous reset */
+ VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
+ vgaHWSeqReset(par, 0); /* clear synchronous reset */
VGAdisablePalette(par);
}
}
-static void vgaHWRestore (struct savagefb_par *par)
+static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
{
int i;
- VGAwMISC (par->MiscOutReg, par);
+ VGAwMISC(reg->MiscOutReg, par);
for (i = 1; i < 5; i++)
- VGAwSEQ (i, par->Sequencer[i], par);
+ VGAwSEQ(i, reg->Sequencer[i], par);
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
CRTC[17] */
- VGAwCR (17, par->CRTC[17] & ~0x80, par);
+ VGAwCR(17, reg->CRTC[17] & ~0x80, par);
for (i = 0; i < 25; i++)
- VGAwCR (i, par->CRTC[i], par);
+ VGAwCR(i, reg->CRTC[i], par);
for (i = 0; i < 9; i++)
- VGAwGR (i, par->Graphics[i], par);
+ VGAwGR(i, reg->Graphics[i], par);
VGAenablePalette(par);
for (i = 0; i < 21; i++)
- VGAwATTR (i, par->Attribute[i], par);
+ VGAwATTR(i, reg->Attribute[i], par);
VGAdisablePalette(par);
}
-static void vgaHWInit (struct fb_var_screeninfo *var,
- struct savagefb_par *par,
- struct xtimings *timings)
+static void vgaHWInit(struct fb_var_screeninfo *var,
+ struct savagefb_par *par,
+ struct xtimings *timings,
+ struct savage_reg *reg)
{
- par->MiscOutReg = 0x23;
+ reg->MiscOutReg = 0x23;
if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
- par->MiscOutReg |= 0x40;
+ reg->MiscOutReg |= 0x40;
if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
- par->MiscOutReg |= 0x80;
+ reg->MiscOutReg |= 0x80;
/*
* Time Sequencer
*/
- par->Sequencer[0x00] = 0x00;
- par->Sequencer[0x01] = 0x01;
- par->Sequencer[0x02] = 0x0F;
- par->Sequencer[0x03] = 0x00; /* Font select */
- par->Sequencer[0x04] = 0x0E; /* Misc */
+ reg->Sequencer[0x00] = 0x00;
+ reg->Sequencer[0x01] = 0x01;
+ reg->Sequencer[0x02] = 0x0F;
+ reg->Sequencer[0x03] = 0x00; /* Font select */
+ reg->Sequencer[0x04] = 0x0E; /* Misc */
/*
* CRTC Controller
*/
- par->CRTC[0x00] = (timings->HTotal >> 3) - 5;
- par->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
- par->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
- par->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
- par->CRTC[0x04] = (timings->HSyncStart >> 3);
- par->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
+ reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
+ reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
+ reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
+ reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
+ reg->CRTC[0x04] = (timings->HSyncStart >> 3);
+ reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
(((timings->HSyncEnd >> 3)) & 0x1f);
- par->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
- par->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
+ reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
+ reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
(((timings->VDisplay - 1) & 0x100) >> 7) |
((timings->VSyncStart & 0x100) >> 6) |
(((timings->VSyncStart - 1) & 0x100) >> 5) |
(((timings->VTotal - 2) & 0x200) >> 4) |
(((timings->VDisplay - 1) & 0x200) >> 3) |
((timings->VSyncStart & 0x200) >> 2);
- par->CRTC[0x08] = 0x00;
- par->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
+ reg->CRTC[0x08] = 0x00;
+ reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
if (timings->dblscan)
- par->CRTC[0x09] |= 0x80;
-
- par->CRTC[0x0a] = 0x00;
- par->CRTC[0x0b] = 0x00;
- par->CRTC[0x0c] = 0x00;
- par->CRTC[0x0d] = 0x00;
- par->CRTC[0x0e] = 0x00;
- par->CRTC[0x0f] = 0x00;
- par->CRTC[0x10] = timings->VSyncStart & 0xff;
- par->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
- par->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
- par->CRTC[0x13] = var->xres_virtual >> 4;
- par->CRTC[0x14] = 0x00;
- par->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
- par->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
- par->CRTC[0x17] = 0xc3;
- par->CRTC[0x18] = 0xff;
+ reg->CRTC[0x09] |= 0x80;
+
+ reg->CRTC[0x0a] = 0x00;
+ reg->CRTC[0x0b] = 0x00;
+ reg->CRTC[0x0c] = 0x00;
+ reg->CRTC[0x0d] = 0x00;
+ reg->CRTC[0x0e] = 0x00;
+ reg->CRTC[0x0f] = 0x00;
+ reg->CRTC[0x10] = timings->VSyncStart & 0xff;
+ reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
+ reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
+ reg->CRTC[0x13] = var->xres_virtual >> 4;
+ reg->CRTC[0x14] = 0x00;
+ reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
+ reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
+ reg->CRTC[0x17] = 0xc3;
+ reg->CRTC[0x18] = 0xff;
/*
* are these unnecessary?
/*
* Graphics Display Controller
*/
- par->Graphics[0x00] = 0x00;
- par->Graphics[0x01] = 0x00;
- par->Graphics[0x02] = 0x00;
- par->Graphics[0x03] = 0x00;
- par->Graphics[0x04] = 0x00;
- par->Graphics[0x05] = 0x40;
- par->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
- par->Graphics[0x07] = 0x0F;
- par->Graphics[0x08] = 0xFF;
-
-
- par->Attribute[0x00] = 0x00; /* standard colormap translation */
- par->Attribute[0x01] = 0x01;
- par->Attribute[0x02] = 0x02;
- par->Attribute[0x03] = 0x03;
- par->Attribute[0x04] = 0x04;
- par->Attribute[0x05] = 0x05;
- par->Attribute[0x06] = 0x06;
- par->Attribute[0x07] = 0x07;
- par->Attribute[0x08] = 0x08;
- par->Attribute[0x09] = 0x09;
- par->Attribute[0x0a] = 0x0A;
- par->Attribute[0x0b] = 0x0B;
- par->Attribute[0x0c] = 0x0C;
- par->Attribute[0x0d] = 0x0D;
- par->Attribute[0x0e] = 0x0E;
- par->Attribute[0x0f] = 0x0F;
- par->Attribute[0x10] = 0x41;
- par->Attribute[0x11] = 0xFF;
- par->Attribute[0x12] = 0x0F;
- par->Attribute[0x13] = 0x00;
- par->Attribute[0x14] = 0x00;
+ reg->Graphics[0x00] = 0x00;
+ reg->Graphics[0x01] = 0x00;
+ reg->Graphics[0x02] = 0x00;
+ reg->Graphics[0x03] = 0x00;
+ reg->Graphics[0x04] = 0x00;
+ reg->Graphics[0x05] = 0x40;
+ reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
+ reg->Graphics[0x07] = 0x0F;
+ reg->Graphics[0x08] = 0xFF;
+
+
+ reg->Attribute[0x00] = 0x00; /* standard colormap translation */
+ reg->Attribute[0x01] = 0x01;
+ reg->Attribute[0x02] = 0x02;
+ reg->Attribute[0x03] = 0x03;
+ reg->Attribute[0x04] = 0x04;
+ reg->Attribute[0x05] = 0x05;
+ reg->Attribute[0x06] = 0x06;
+ reg->Attribute[0x07] = 0x07;
+ reg->Attribute[0x08] = 0x08;
+ reg->Attribute[0x09] = 0x09;
+ reg->Attribute[0x0a] = 0x0A;
+ reg->Attribute[0x0b] = 0x0B;
+ reg->Attribute[0x0c] = 0x0C;
+ reg->Attribute[0x0d] = 0x0D;
+ reg->Attribute[0x0e] = 0x0E;
+ reg->Attribute[0x0f] = 0x0F;
+ reg->Attribute[0x10] = 0x41;
+ reg->Attribute[0x11] = 0xFF;
+ reg->Attribute[0x12] = 0x0F;
+ reg->Attribute[0x13] = 0x00;
+ reg->Attribute[0x14] = 0x00;
}
/* -------------------- Hardware specific routines ------------------------- */
while ((savage_in32(0x48C60, par) & 0x009fffff));
}
-
+#ifdef CONFIG_FB_SAVAGE_ACCEL
static void
-SavageSetup2DEngine (struct savagefb_par *par)
+SavageSetup2DEngine(struct savagefb_par *par)
{
unsigned long GlobalBitmapDescriptor;
GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
- BCI_BD_SET_BPP (GlobalBitmapDescriptor, par->depth);
- BCI_BD_SET_STRIDE (GlobalBitmapDescriptor, par->vwidth);
+ BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
+ BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
switch(par->chip) {
case S3_SAVAGE3D:
vga_out8(0x3d5, 0x0c, par);
/* Set stride to use GBD. */
- vga_out8 (0x3d4, 0x50, par);
- vga_out8 (0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
+ vga_out8(0x3d4, 0x50, par);
+ vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
/* Enable 2D engine. */
- vga_out8 (0x3d4, 0x40, par);
- vga_out8 (0x3d5, 0x01, par);
+ vga_out8(0x3d4, 0x40, par);
+ vga_out8(0x3d5, 0x01, par);
- savage_out32 (MONO_PAT_0, ~0, par);
- savage_out32 (MONO_PAT_1, ~0, par);
+ savage_out32(MONO_PAT_0, ~0, par);
+ savage_out32(MONO_PAT_1, ~0, par);
/* Setup plane masks */
- savage_out32 (0x8128, ~0, par); /* enable all write planes */
- savage_out32 (0x812C, ~0, par); /* enable all read planes */
- savage_out16 (0x8134, 0x27, par);
- savage_out16 (0x8136, 0x07, par);
+ savage_out32(0x8128, ~0, par); /* enable all write planes */
+ savage_out32(0x812C, ~0, par); /* enable all read planes */
+ savage_out16(0x8134, 0x27, par);
+ savage_out16(0x8136, 0x07, par);
/* Now set the GBD */
par->bci_ptr = 0;
- par->SavageWaitFifo (par, 4);
+ par->SavageWaitFifo(par, 4);
- BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD1 );
- BCI_SEND( 0 );
- BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD2 );
- BCI_SEND( GlobalBitmapDescriptor );
+ BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
+ BCI_SEND(0);
+ BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
+ BCI_SEND(GlobalBitmapDescriptor);
}
+static void savagefb_set_clip(struct fb_info *info)
+{
+ struct savagefb_par *par = info->par;
+ int cmd;
+
+ cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
+ par->bci_ptr = 0;
+ par->SavageWaitFifo(par,3);
+ BCI_SEND(cmd);
+ BCI_SEND(BCI_CLIP_TL(0, 0));
+ BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
+}
+#else
+static void SavageSetup2DEngine(struct savagefb_par *par) {}
+
+#endif
static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
int min_n2, int max_n2, long freq_min,
unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
if (freq < freq_min / (1 << max_n2)) {
- printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
+ printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
freq = freq_min / (1 << max_n2);
}
if (freq > freq_max / (1 << min_n2)) {
- printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
+ printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
freq = freq_max / (1 << min_n2);
}
BASE_FREQ;
if (m < min_m + 2 || m > 127+2)
continue;
- if((m * BASE_FREQ >= freq_min * n1) &&
- (m * BASE_FREQ <= freq_max * n1)) {
+ if ((m * BASE_FREQ >= freq_min * n1) &&
+ (m * BASE_FREQ <= freq_max * n1)) {
diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
- if(diff < 0)
+ if (diff < 0)
diff = -diff;
- if(diff < best_diff) {
+ if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
}
}
- if(max_n1 == 63)
+ if (max_n1 == 63)
*ndiv = (best_n1 - 2) | (best_n2 << 6);
else
*ndiv = (best_n1 - 2) | (best_n2 << 5);
int vgaCRReg = 0x3d5;
printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
- "xF" );
+ "xF");
- for( i = 0; i < 0x70; i++ ) {
- if( !(i % 16) )
- printk(KERN_DEBUG "\nSR%xx ", i >> 4 );
- vga_out8( 0x3c4, i, par);
- printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par) );
+ for (i = 0; i < 0x70; i++) {
+ if (!(i % 16))
+ printk(KERN_DEBUG "\nSR%xx ", i >> 4);
+ vga_out8(0x3c4, i, par);
+ printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
}
printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
- "xD xE xF" );
+ "xD xE xF");
- for( i = 0; i < 0xB7; i++ ) {
- if( !(i % 16) )
- printk(KERN_DEBUG "\nCR%xx ", i >> 4 );
- vga_out8( vgaCRIndex, i, par);
- printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par) );
+ for (i = 0; i < 0xB7; i++) {
+ if (!(i % 16))
+ printk(KERN_DEBUG "\nCR%xx ", i >> 4);
+ vga_out8(vgaCRIndex, i, par);
+ printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
}
printk(KERN_DEBUG "\n\n");
/* --------------------------------------------------------------------- */
-static void savage_get_default_par(struct savagefb_par *par)
+static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
{
unsigned char cr3a, cr53, cr66;
- vga_out16 (0x3d4, 0x4838, par);
- vga_out16 (0x3d4, 0xa039, par);
- vga_out16 (0x3c4, 0x0608, par);
-
- vga_out8 (0x3d4, 0x66, par);
- cr66 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr66 | 0x80, par);
- vga_out8 (0x3d4, 0x3a, par);
- cr3a = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr3a | 0x80, par);
- vga_out8 (0x3d4, 0x53, par);
- cr53 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr53 & 0x7f, par);
-
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, cr66, par);
- vga_out8 (0x3d4, 0x3a, par);
- vga_out8 (0x3d5, cr3a, par);
-
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, cr66, par);
- vga_out8 (0x3d4, 0x3a, par);
- vga_out8 (0x3d5, cr3a, par);
+ vga_out16(0x3d4, 0x4838, par);
+ vga_out16(0x3d4, 0xa039, par);
+ vga_out16(0x3c4, 0x0608, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x80, par);
+ vga_out8(0x3d4, 0x3a, par);
+ cr3a = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3a | 0x80, par);
+ vga_out8(0x3d4, 0x53, par);
+ cr53 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr53 & 0x7f, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
/* unlock extended seq regs */
- vga_out8 (0x3c4, 0x08, par);
- par->SR08 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c5, 0x06, par);
+ vga_out8(0x3c4, 0x08, par);
+ reg->SR08 = vga_in8(0x3c5, par);
+ vga_out8(0x3c5, 0x06, par);
/* now save all the extended regs we need */
- vga_out8 (0x3d4, 0x31, par);
- par->CR31 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x32, par);
- par->CR32 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x34, par);
- par->CR34 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x36, par);
- par->CR36 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x3a, par);
- par->CR3A = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x40, par);
- par->CR40 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x42, par);
- par->CR42 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x45, par);
- par->CR45 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x50, par);
- par->CR50 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x51, par);
- par->CR51 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x53, par);
- par->CR53 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x58, par);
- par->CR58 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x60, par);
- par->CR60 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x66, par);
- par->CR66 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x67, par);
- par->CR67 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x68, par);
- par->CR68 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x69, par);
- par->CR69 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x6f, par);
- par->CR6F = vga_in8 (0x3d5, par);
-
- vga_out8 (0x3d4, 0x33, par);
- par->CR33 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x86, par);
- par->CR86 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x88, par);
- par->CR88 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x90, par);
- par->CR90 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x91, par);
- par->CR91 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0xb0, par);
- par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
+ vga_out8(0x3d4, 0x31, par);
+ reg->CR31 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x32, par);
+ reg->CR32 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x34, par);
+ reg->CR34 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x36, par);
+ reg->CR36 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x3a, par);
+ reg->CR3A = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x40, par);
+ reg->CR40 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x42, par);
+ reg->CR42 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x45, par);
+ reg->CR45 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x50, par);
+ reg->CR50 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x51, par);
+ reg->CR51 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x53, par);
+ reg->CR53 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x58, par);
+ reg->CR58 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x60, par);
+ reg->CR60 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x66, par);
+ reg->CR66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x67, par);
+ reg->CR67 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x68, par);
+ reg->CR68 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x69, par);
+ reg->CR69 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x6f, par);
+ reg->CR6F = vga_in8(0x3d5, par);
+
+ vga_out8(0x3d4, 0x33, par);
+ reg->CR33 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x86, par);
+ reg->CR86 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x88, par);
+ reg->CR88 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x90, par);
+ reg->CR90 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x91, par);
+ reg->CR91 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0xb0, par);
+ reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
+
+ /* extended mode timing regs */
+ vga_out8(0x3d4, 0x3b, par);
+ reg->CR3B = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x3c, par);
+ reg->CR3C = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x43, par);
+ reg->CR43 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x5d, par);
+ reg->CR5D = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x5e, par);
+ reg->CR5E = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x65, par);
+ reg->CR65 = vga_in8(0x3d5, par);
+
+ /* save seq extended regs for DCLK PLL programming */
+ vga_out8(0x3c4, 0x0e, par);
+ reg->SR0E = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x0f, par);
+ reg->SR0F = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x10, par);
+ reg->SR10 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x11, par);
+ reg->SR11 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x12, par);
+ reg->SR12 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x13, par);
+ reg->SR13 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x29, par);
+ reg->SR29 = vga_in8(0x3c5, par);
+
+ vga_out8(0x3c4, 0x15, par);
+ reg->SR15 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x30, par);
+ reg->SR30 = vga_in8(0x3c5, par);
+ vga_out8(0x3c4, 0x18, par);
+ reg->SR18 = vga_in8(0x3c5, par);
+
+ /* Save flat panel expansion regsters. */
+ if (par->chip == S3_SAVAGE_MX) {
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ vga_out8(0x3c4, 0x54+i, par);
+ reg->SR54[i] = vga_in8(0x3c5, par);
+ }
+ }
+
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x80, par);
+ vga_out8(0x3d4, 0x3a, par);
+ cr3a = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3a | 0x80, par);
+
+ /* now save MIU regs */
+ if (par->chip != S3_SAVAGE_MX) {
+ reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
+ reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
+ reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
+ reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
+ }
+
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+}
+
+static void savage_set_default_par(struct savagefb_par *par,
+ struct savage_reg *reg)
+{
+ unsigned char cr3a, cr53, cr66;
+
+ vga_out16(0x3d4, 0x4838, par);
+ vga_out16(0x3d4, 0xa039, par);
+ vga_out16(0x3c4, 0x0608, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x80, par);
+ vga_out8(0x3d4, 0x3a, par);
+ cr3a = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3a | 0x80, par);
+ vga_out8(0x3d4, 0x53, par);
+ cr53 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr53 & 0x7f, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
+
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
+
+ /* unlock extended seq regs */
+ vga_out8(0x3c4, 0x08, par);
+ vga_out8(0x3c5, reg->SR08, par);
+ vga_out8(0x3c5, 0x06, par);
+
+ /* now restore all the extended regs we need */
+ vga_out8(0x3d4, 0x31, par);
+ vga_out8(0x3d5, reg->CR31, par);
+ vga_out8(0x3d4, 0x32, par);
+ vga_out8(0x3d5, reg->CR32, par);
+ vga_out8(0x3d4, 0x34, par);
+ vga_out8(0x3d5, reg->CR34, par);
+ vga_out8(0x3d4, 0x36, par);
+ vga_out8(0x3d5,reg->CR36, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, reg->CR3A, par);
+ vga_out8(0x3d4, 0x40, par);
+ vga_out8(0x3d5, reg->CR40, par);
+ vga_out8(0x3d4, 0x42, par);
+ vga_out8(0x3d5, reg->CR42, par);
+ vga_out8(0x3d4, 0x45, par);
+ vga_out8(0x3d5, reg->CR45, par);
+ vga_out8(0x3d4, 0x50, par);
+ vga_out8(0x3d5, reg->CR50, par);
+ vga_out8(0x3d4, 0x51, par);
+ vga_out8(0x3d5, reg->CR51, par);
+ vga_out8(0x3d4, 0x53, par);
+ vga_out8(0x3d5, reg->CR53, par);
+ vga_out8(0x3d4, 0x58, par);
+ vga_out8(0x3d5, reg->CR58, par);
+ vga_out8(0x3d4, 0x60, par);
+ vga_out8(0x3d5, reg->CR60, par);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, reg->CR66, par);
+ vga_out8(0x3d4, 0x67, par);
+ vga_out8(0x3d5, reg->CR67, par);
+ vga_out8(0x3d4, 0x68, par);
+ vga_out8(0x3d5, reg->CR68, par);
+ vga_out8(0x3d4, 0x69, par);
+ vga_out8(0x3d5, reg->CR69, par);
+ vga_out8(0x3d4, 0x6f, par);
+ vga_out8(0x3d5, reg->CR6F, par);
+
+ vga_out8(0x3d4, 0x33, par);
+ vga_out8(0x3d5, reg->CR33, par);
+ vga_out8(0x3d4, 0x86, par);
+ vga_out8(0x3d5, reg->CR86, par);
+ vga_out8(0x3d4, 0x88, par);
+ vga_out8(0x3d5, reg->CR88, par);
+ vga_out8(0x3d4, 0x90, par);
+ vga_out8(0x3d5, reg->CR90, par);
+ vga_out8(0x3d4, 0x91, par);
+ vga_out8(0x3d5, reg->CR91, par);
+ vga_out8(0x3d4, 0xb0, par);
+ vga_out8(0x3d5, reg->CRB0, par);
/* extended mode timing regs */
- vga_out8 (0x3d4, 0x3b, par);
- par->CR3B = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x3c, par);
- par->CR3C = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x43, par);
- par->CR43 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x5d, par);
- par->CR5D = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x5e, par);
- par->CR5E = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x65, par);
- par->CR65 = vga_in8 (0x3d5, par);
+ vga_out8(0x3d4, 0x3b, par);
+ vga_out8(0x3d5, reg->CR3B, par);
+ vga_out8(0x3d4, 0x3c, par);
+ vga_out8(0x3d5, reg->CR3C, par);
+ vga_out8(0x3d4, 0x43, par);
+ vga_out8(0x3d5, reg->CR43, par);
+ vga_out8(0x3d4, 0x5d, par);
+ vga_out8(0x3d5, reg->CR5D, par);
+ vga_out8(0x3d4, 0x5e, par);
+ vga_out8(0x3d5, reg->CR5E, par);
+ vga_out8(0x3d4, 0x65, par);
+ vga_out8(0x3d5, reg->CR65, par);
/* save seq extended regs for DCLK PLL programming */
- vga_out8 (0x3c4, 0x0e, par);
- par->SR0E = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x0f, par);
- par->SR0F = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x10, par);
- par->SR10 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x11, par);
- par->SR11 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x12, par);
- par->SR12 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x13, par);
- par->SR13 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x29, par);
- par->SR29 = vga_in8 (0x3c5, par);
-
- vga_out8 (0x3c4, 0x15, par);
- par->SR15 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x30, par);
- par->SR30 = vga_in8 (0x3c5, par);
- vga_out8 (0x3c4, 0x18, par);
- par->SR18 = vga_in8 (0x3c5, par);
+ vga_out8(0x3c4, 0x0e, par);
+ vga_out8(0x3c5, reg->SR0E, par);
+ vga_out8(0x3c4, 0x0f, par);
+ vga_out8(0x3c5, reg->SR0F, par);
+ vga_out8(0x3c4, 0x10, par);
+ vga_out8(0x3c5, reg->SR10, par);
+ vga_out8(0x3c4, 0x11, par);
+ vga_out8(0x3c5, reg->SR11, par);
+ vga_out8(0x3c4, 0x12, par);
+ vga_out8(0x3c5, reg->SR12, par);
+ vga_out8(0x3c4, 0x13, par);
+ vga_out8(0x3c5, reg->SR13, par);
+ vga_out8(0x3c4, 0x29, par);
+ vga_out8(0x3c5, reg->SR29, par);
+
+ vga_out8(0x3c4, 0x15, par);
+ vga_out8(0x3c5, reg->SR15, par);
+ vga_out8(0x3c4, 0x30, par);
+ vga_out8(0x3c5, reg->SR30, par);
+ vga_out8(0x3c4, 0x18, par);
+ vga_out8(0x3c5, reg->SR18, par);
/* Save flat panel expansion regsters. */
if (par->chip == S3_SAVAGE_MX) {
int i;
for (i = 0; i < 8; i++) {
- vga_out8 (0x3c4, 0x54+i, par);
- par->SR54[i] = vga_in8 (0x3c5, par);
+ vga_out8(0x3c4, 0x54+i, par);
+ vga_out8(0x3c5, reg->SR54[i], par);
}
}
- vga_out8 (0x3d4, 0x66, par);
- cr66 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr66 | 0x80, par);
- vga_out8 (0x3d4, 0x3a, par);
- cr3a = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr3a | 0x80, par);
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x80, par);
+ vga_out8(0x3d4, 0x3a, par);
+ cr3a = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3a | 0x80, par);
/* now save MIU regs */
if (par->chip != S3_SAVAGE_MX) {
- par->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
- par->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
- par->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
- par->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
+ savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
+ savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
+ savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
+ savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
}
- vga_out8 (0x3d4, 0x3a, par);
- vga_out8 (0x3d5, cr3a, par);
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
}
static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
var->vmode = modedb->vmode;
}
-static int savagefb_check_var (struct fb_var_screeninfo *var,
- struct fb_info *info)
+static int savagefb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
{
struct savagefb_par *par = info->par;
int memlen, vramlen, mode_valid = 0;
if (par->SavagePanelWidth &&
(var->xres > par->SavagePanelWidth ||
var->yres > par->SavagePanelHeight)) {
- printk (KERN_INFO "Mode (%dx%d) larger than the LCD panel "
- "(%dx%d)\n", var->xres, var->yres,
- par->SavagePanelWidth,
- par->SavagePanelHeight);
+ printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
+ "(%dx%d)\n", var->xres, var->yres,
+ par->SavagePanelWidth,
+ par->SavagePanelHeight);
return -1;
}
}
-static int savagefb_decode_var (struct fb_var_screeninfo *var,
- struct savagefb_par *par)
+static int savagefb_decode_var(struct fb_var_screeninfo *var,
+ struct savagefb_par *par,
+ struct savage_reg *reg)
{
struct xtimings timings;
int width, dclk, i, j; /*, refresh; */
DBG("savagefb_decode_var");
- memset (&timings, 0, sizeof(timings));
+ memset(&timings, 0, sizeof(timings));
if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
timings.Clock = 1000000000 / pixclock;
* This will allocate the datastructure and initialize all of the
* generic VGA registers.
*/
- vgaHWInit (var, par, &timings);
+ vgaHWInit(var, par, &timings, reg);
/* We need to set CR67 whether or not we use the BIOS. */
dclk = timings.Clock;
- par->CR67 = 0x00;
+ reg->CR67 = 0x00;
- switch( var->bits_per_pixel ) {
+ switch(var->bits_per_pixel) {
case 8:
- if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) )
- par->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
+ if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
+ reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
else
- par->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
+ reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
break;
case 15:
- if ( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
- ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
- par->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
+ if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
+ ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
+ reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
else
- par->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
+ reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
break;
case 16:
- if( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
- ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
- par->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
+ if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
+ ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
+ reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
else
- par->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
+ reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
break;
case 24:
- par->CR67 = 0x70;
+ reg->CR67 = 0x70;
break;
case 32:
- par->CR67 = 0xd0;
+ reg->CR67 = 0xd0;
break;
}
* match. Fall back to traditional register-crunching.
*/
- vga_out8 (0x3d4, 0x3a, par);
- tmp = vga_in8 (0x3d5, par);
+ vga_out8(0x3d4, 0x3a, par);
+ tmp = vga_in8(0x3d5, par);
if (1 /*FIXME:psav->pci_burst*/)
- par->CR3A = (tmp & 0x7f) | 0x15;
+ reg->CR3A = (tmp & 0x7f) | 0x15;
else
- par->CR3A = tmp | 0x95;
+ reg->CR3A = tmp | 0x95;
- par->CR53 = 0x00;
- par->CR31 = 0x8c;
- par->CR66 = 0x89;
+ reg->CR53 = 0x00;
+ reg->CR31 = 0x8c;
+ reg->CR66 = 0x89;
- vga_out8 (0x3d4, 0x58, par);
- par->CR58 = vga_in8 (0x3d5, par) & 0x80;
- par->CR58 |= 0x13;
+ vga_out8(0x3d4, 0x58, par);
+ reg->CR58 = vga_in8(0x3d5, par) & 0x80;
+ reg->CR58 |= 0x13;
- par->SR15 = 0x03 | 0x80;
- par->SR18 = 0x00;
- par->CR43 = par->CR45 = par->CR65 = 0x00;
+ reg->SR15 = 0x03 | 0x80;
+ reg->SR18 = 0x00;
+ reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
- vga_out8 (0x3d4, 0x40, par);
- par->CR40 = vga_in8 (0x3d5, par) & ~0x01;
+ vga_out8(0x3d4, 0x40, par);
+ reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
- par->MMPR0 = 0x010400;
- par->MMPR1 = 0x00;
- par->MMPR2 = 0x0808;
- par->MMPR3 = 0x08080810;
+ reg->MMPR0 = 0x010400;
+ reg->MMPR1 = 0x00;
+ reg->MMPR2 = 0x0808;
+ reg->MMPR3 = 0x08080810;
- SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
+ SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
/* m = 107; n = 4; r = 2; */
if (par->MCLK <= 0) {
- par->SR10 = 255;
- par->SR11 = 255;
+ reg->SR10 = 255;
+ reg->SR11 = 255;
} else {
- common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
- &par->SR11, &par->SR10);
- /* par->SR10 = 80; // MCLK == 286000 */
- /* par->SR11 = 125; */
+ common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
+ ®->SR11, ®->SR10);
+ /* reg->SR10 = 80; // MCLK == 286000 */
+ /* reg->SR11 = 125; */
}
- par->SR12 = (r << 6) | (n & 0x3f);
- par->SR13 = m & 0xff;
- par->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
+ reg->SR12 = (r << 6) | (n & 0x3f);
+ reg->SR13 = m & 0xff;
+ reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
if (var->bits_per_pixel < 24)
- par->MMPR0 -= 0x8000;
+ reg->MMPR0 -= 0x8000;
else
- par->MMPR0 -= 0x4000;
+ reg->MMPR0 -= 0x4000;
if (timings.interlaced)
- par->CR42 = 0x20;
+ reg->CR42 = 0x20;
else
- par->CR42 = 0x00;
+ reg->CR42 = 0x00;
- par->CR34 = 0x10; /* display fifo */
+ reg->CR34 = 0x10; /* display fifo */
i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
i |= 0x20;
- j = (par->CRTC[0] + ((i & 0x01) << 8) +
- par->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
+ j = (reg->CRTC[0] + ((i & 0x01) << 8) +
+ reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
- if (j - (par->CRTC[4] + ((i & 0x10) << 4)) < 4) {
- if (par->CRTC[4] + ((i & 0x10) << 4) + 4 <=
- par->CRTC[0] + ((i & 0x01) << 8))
- j = par->CRTC[4] + ((i & 0x10) << 4) + 4;
+ if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
+ if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
+ reg->CRTC[0] + ((i & 0x01) << 8))
+ j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
else
- j = par->CRTC[0] + ((i & 0x01) << 8) + 1;
+ j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
}
- par->CR3B = j & 0xff;
+ reg->CR3B = j & 0xff;
i |= (j & 0x100) >> 2;
- par->CR3C = (par->CRTC[0] + ((i & 0x01) << 8)) / 2;
- par->CR5D = i;
- par->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
+ reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
+ reg->CR5D = i;
+ reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
(((timings.VDisplay - 1) & 0x400) >> 9) |
(((timings.VSyncStart) & 0x400) >> 8) |
(((timings.VSyncStart) & 0x400) >> 6) | 0x40;
width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
- par->CR91 = par->CRTC[19] = 0xff & width;
- par->CR51 = (0x300 & width) >> 4;
- par->CR90 = 0x80 | (width >> 8);
- par->MiscOutReg |= 0x0c;
+ reg->CR91 = reg->CRTC[19] = 0xff & width;
+ reg->CR51 = (0x300 & width) >> 4;
+ reg->CR90 = 0x80 | (width >> 8);
+ reg->MiscOutReg |= 0x0c;
/* Set frame buffer description. */
if (var->bits_per_pixel <= 8)
- par->CR50 = 0;
+ reg->CR50 = 0;
else if (var->bits_per_pixel <= 16)
- par->CR50 = 0x10;
+ reg->CR50 = 0x10;
else
- par->CR50 = 0x30;
+ reg->CR50 = 0x30;
if (var->xres_virtual <= 640)
- par->CR50 |= 0x40;
+ reg->CR50 |= 0x40;
else if (var->xres_virtual == 800)
- par->CR50 |= 0x80;
+ reg->CR50 |= 0x80;
else if (var->xres_virtual == 1024)
- par->CR50 |= 0x00;
+ reg->CR50 |= 0x00;
else if (var->xres_virtual == 1152)
- par->CR50 |= 0x01;
+ reg->CR50 |= 0x01;
else if (var->xres_virtual == 1280)
- par->CR50 |= 0xc0;
+ reg->CR50 |= 0xc0;
else if (var->xres_virtual == 1600)
- par->CR50 |= 0x81;
+ reg->CR50 |= 0x81;
else
- par->CR50 |= 0xc1; /* Use GBD */
+ reg->CR50 |= 0xc1; /* Use GBD */
- if( par->chip == S3_SAVAGE2000 )
- par->CR33 = 0x08;
+ if (par->chip == S3_SAVAGE2000)
+ reg->CR33 = 0x08;
else
- par->CR33 = 0x20;
+ reg->CR33 = 0x20;
- par->CRTC[0x17] = 0xeb;
+ reg->CRTC[0x17] = 0xeb;
- par->CR67 |= 1;
+ reg->CR67 |= 1;
vga_out8(0x3d4, 0x36, par);
- par->CR36 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x68, par);
- par->CR68 = vga_in8 (0x3d5, par);
- par->CR69 = 0;
- vga_out8 (0x3d4, 0x6f, par);
- par->CR6F = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x86, par);
- par->CR86 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d4, 0x88, par);
- par->CR88 = vga_in8 (0x3d5, par) | 0x08;
- vga_out8 (0x3d4, 0xb0, par);
- par->CRB0 = vga_in8 (0x3d5, par) | 0x80;
+ reg->CR36 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x68, par);
+ reg->CR68 = vga_in8(0x3d5, par);
+ reg->CR69 = 0;
+ vga_out8(0x3d4, 0x6f, par);
+ reg->CR6F = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x86, par);
+ reg->CR86 = vga_in8(0x3d5, par);
+ vga_out8(0x3d4, 0x88, par);
+ reg->CR88 = vga_in8(0x3d5, par) | 0x08;
+ vga_out8(0x3d4, 0xb0, par);
+ reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
return 0;
}
switch (info->var.bits_per_pixel) {
case 8:
- vga_out8 (0x3c8, regno, par);
+ vga_out8(0x3c8, regno, par);
- vga_out8 (0x3c9, red >> 10, par);
- vga_out8 (0x3c9, green >> 10, par);
- vga_out8 (0x3c9, blue >> 10, par);
+ vga_out8(0x3c9, red >> 10, par);
+ vga_out8(0x3c9, green >> 10, par);
+ vga_out8(0x3c9, blue >> 10, par);
break;
case 16:
return 0;
}
-static void savagefb_set_par_int (struct savagefb_par *par)
+static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
{
unsigned char tmp, cr3a, cr66, cr67;
- DBG ("savagefb_set_par_int");
+ DBG("savagefb_set_par_int");
- par->SavageWaitIdle (par);
+ par->SavageWaitIdle(par);
- vga_out8 (0x3c2, 0x23, par);
+ vga_out8(0x3c2, 0x23, par);
- vga_out16 (0x3d4, 0x4838, par);
- vga_out16 (0x3d4, 0xa539, par);
- vga_out16 (0x3c4, 0x0608, par);
+ vga_out16(0x3d4, 0x4838, par);
+ vga_out16(0x3d4, 0xa539, par);
+ vga_out16(0x3c4, 0x0608, par);
- vgaHWProtect (par, 1);
+ vgaHWProtect(par, 1);
/*
* Some Savage/MX and /IX systems go nuts when trying to exit the
*/
VerticalRetraceWait(par);
- vga_out8 (0x3d4, 0x67, par);
- cr67 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
+ vga_out8(0x3d4, 0x67, par);
+ cr67 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
- vga_out8 (0x3d4, 0x23, par);
- vga_out8 (0x3d5, 0x00, par);
- vga_out8 (0x3d4, 0x26, par);
- vga_out8 (0x3d5, 0x00, par);
+ vga_out8(0x3d4, 0x23, par);
+ vga_out8(0x3d5, 0x00, par);
+ vga_out8(0x3d4, 0x26, par);
+ vga_out8(0x3d5, 0x00, par);
/* restore extended regs */
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, par->CR66, par);
- vga_out8 (0x3d4, 0x3a, par);
- vga_out8 (0x3d5, par->CR3A, par);
- vga_out8 (0x3d4, 0x31, par);
- vga_out8 (0x3d5, par->CR31, par);
- vga_out8 (0x3d4, 0x32, par);
- vga_out8 (0x3d5, par->CR32, par);
- vga_out8 (0x3d4, 0x58, par);
- vga_out8 (0x3d5, par->CR58, par);
- vga_out8 (0x3d4, 0x53, par);
- vga_out8 (0x3d5, par->CR53 & 0x7f, par);
-
- vga_out16 (0x3c4, 0x0608, par);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, reg->CR66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, reg->CR3A, par);
+ vga_out8(0x3d4, 0x31, par);
+ vga_out8(0x3d5, reg->CR31, par);
+ vga_out8(0x3d4, 0x32, par);
+ vga_out8(0x3d5, reg->CR32, par);
+ vga_out8(0x3d4, 0x58, par);
+ vga_out8(0x3d5, reg->CR58, par);
+ vga_out8(0x3d4, 0x53, par);
+ vga_out8(0x3d5, reg->CR53 & 0x7f, par);
+
+ vga_out16(0x3c4, 0x0608, par);
/* Restore DCLK registers. */
- vga_out8 (0x3c4, 0x0e, par);
- vga_out8 (0x3c5, par->SR0E, par);
- vga_out8 (0x3c4, 0x0f, par);
- vga_out8 (0x3c5, par->SR0F, par);
- vga_out8 (0x3c4, 0x29, par);
- vga_out8 (0x3c5, par->SR29, par);
- vga_out8 (0x3c4, 0x15, par);
- vga_out8 (0x3c5, par->SR15, par);
+ vga_out8(0x3c4, 0x0e, par);
+ vga_out8(0x3c5, reg->SR0E, par);
+ vga_out8(0x3c4, 0x0f, par);
+ vga_out8(0x3c5, reg->SR0F, par);
+ vga_out8(0x3c4, 0x29, par);
+ vga_out8(0x3c5, reg->SR29, par);
+ vga_out8(0x3c4, 0x15, par);
+ vga_out8(0x3c5, reg->SR15, par);
/* Restore flat panel expansion regsters. */
- if( par->chip == S3_SAVAGE_MX ) {
+ if (par->chip == S3_SAVAGE_MX) {
int i;
- for( i = 0; i < 8; i++ ) {
- vga_out8 (0x3c4, 0x54+i, par);
- vga_out8 (0x3c5, par->SR54[i], par);
+ for (i = 0; i < 8; i++) {
+ vga_out8(0x3c4, 0x54+i, par);
+ vga_out8(0x3c5, reg->SR54[i], par);
}
}
- vgaHWRestore (par);
+ vgaHWRestore (par, reg);
/* extended mode timing registers */
- vga_out8 (0x3d4, 0x53, par);
- vga_out8 (0x3d5, par->CR53, par);
- vga_out8 (0x3d4, 0x5d, par);
- vga_out8 (0x3d5, par->CR5D, par);
- vga_out8 (0x3d4, 0x5e, par);
- vga_out8 (0x3d5, par->CR5E, par);
- vga_out8 (0x3d4, 0x3b, par);
- vga_out8 (0x3d5, par->CR3B, par);
- vga_out8 (0x3d4, 0x3c, par);
- vga_out8 (0x3d5, par->CR3C, par);
- vga_out8 (0x3d4, 0x43, par);
- vga_out8 (0x3d5, par->CR43, par);
- vga_out8 (0x3d4, 0x65, par);
- vga_out8 (0x3d5, par->CR65, par);
+ vga_out8(0x3d4, 0x53, par);
+ vga_out8(0x3d5, reg->CR53, par);
+ vga_out8(0x3d4, 0x5d, par);
+ vga_out8(0x3d5, reg->CR5D, par);
+ vga_out8(0x3d4, 0x5e, par);
+ vga_out8(0x3d5, reg->CR5E, par);
+ vga_out8(0x3d4, 0x3b, par);
+ vga_out8(0x3d5, reg->CR3B, par);
+ vga_out8(0x3d4, 0x3c, par);
+ vga_out8(0x3d5, reg->CR3C, par);
+ vga_out8(0x3d4, 0x43, par);
+ vga_out8(0x3d5, reg->CR43, par);
+ vga_out8(0x3d4, 0x65, par);
+ vga_out8(0x3d5, reg->CR65, par);
/* restore the desired video mode with cr67 */
- vga_out8 (0x3d4, 0x67, par);
+ vga_out8(0x3d4, 0x67, par);
/* following part not present in X11 driver */
- cr67 = vga_in8 (0x3d5, par) & 0xf;
- vga_out8 (0x3d5, 0x50 | cr67, par);
- udelay (10000);
- vga_out8 (0x3d4, 0x67, par);
+ cr67 = vga_in8(0x3d5, par) & 0xf;
+ vga_out8(0x3d5, 0x50 | cr67, par);
+ udelay(10000);
+ vga_out8(0x3d4, 0x67, par);
/* end of part */
- vga_out8 (0x3d5, par->CR67 & ~0x0c, par);
+ vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
/* other mode timing and extended regs */
- vga_out8 (0x3d4, 0x34, par);
- vga_out8 (0x3d5, par->CR34, par);
- vga_out8 (0x3d4, 0x40, par);
- vga_out8 (0x3d5, par->CR40, par);
- vga_out8 (0x3d4, 0x42, par);
- vga_out8 (0x3d5, par->CR42, par);
- vga_out8 (0x3d4, 0x45, par);
- vga_out8 (0x3d5, par->CR45, par);
- vga_out8 (0x3d4, 0x50, par);
- vga_out8 (0x3d5, par->CR50, par);
- vga_out8 (0x3d4, 0x51, par);
- vga_out8 (0x3d5, par->CR51, par);
+ vga_out8(0x3d4, 0x34, par);
+ vga_out8(0x3d5, reg->CR34, par);
+ vga_out8(0x3d4, 0x40, par);
+ vga_out8(0x3d5, reg->CR40, par);
+ vga_out8(0x3d4, 0x42, par);
+ vga_out8(0x3d5, reg->CR42, par);
+ vga_out8(0x3d4, 0x45, par);
+ vga_out8(0x3d5, reg->CR45, par);
+ vga_out8(0x3d4, 0x50, par);
+ vga_out8(0x3d5, reg->CR50, par);
+ vga_out8(0x3d4, 0x51, par);
+ vga_out8(0x3d5, reg->CR51, par);
/* memory timings */
- vga_out8 (0x3d4, 0x36, par);
- vga_out8 (0x3d5, par->CR36, par);
- vga_out8 (0x3d4, 0x60, par);
- vga_out8 (0x3d5, par->CR60, par);
- vga_out8 (0x3d4, 0x68, par);
- vga_out8 (0x3d5, par->CR68, par);
- vga_out8 (0x3d4, 0x69, par);
- vga_out8 (0x3d5, par->CR69, par);
- vga_out8 (0x3d4, 0x6f, par);
- vga_out8 (0x3d5, par->CR6F, par);
-
- vga_out8 (0x3d4, 0x33, par);
- vga_out8 (0x3d5, par->CR33, par);
- vga_out8 (0x3d4, 0x86, par);
- vga_out8 (0x3d5, par->CR86, par);
- vga_out8 (0x3d4, 0x88, par);
- vga_out8 (0x3d5, par->CR88, par);
- vga_out8 (0x3d4, 0x90, par);
- vga_out8 (0x3d5, par->CR90, par);
- vga_out8 (0x3d4, 0x91, par);
- vga_out8 (0x3d5, par->CR91, par);
+ vga_out8(0x3d4, 0x36, par);
+ vga_out8(0x3d5, reg->CR36, par);
+ vga_out8(0x3d4, 0x60, par);
+ vga_out8(0x3d5, reg->CR60, par);
+ vga_out8(0x3d4, 0x68, par);
+ vga_out8(0x3d5, reg->CR68, par);
+ vga_out8(0x3d4, 0x69, par);
+ vga_out8(0x3d5, reg->CR69, par);
+ vga_out8(0x3d4, 0x6f, par);
+ vga_out8(0x3d5, reg->CR6F, par);
+
+ vga_out8(0x3d4, 0x33, par);
+ vga_out8(0x3d5, reg->CR33, par);
+ vga_out8(0x3d4, 0x86, par);
+ vga_out8(0x3d5, reg->CR86, par);
+ vga_out8(0x3d4, 0x88, par);
+ vga_out8(0x3d5, reg->CR88, par);
+ vga_out8(0x3d4, 0x90, par);
+ vga_out8(0x3d5, reg->CR90, par);
+ vga_out8(0x3d4, 0x91, par);
+ vga_out8(0x3d5, reg->CR91, par);
if (par->chip == S3_SAVAGE4) {
- vga_out8 (0x3d4, 0xb0, par);
- vga_out8 (0x3d5, par->CRB0, par);
+ vga_out8(0x3d4, 0xb0, par);
+ vga_out8(0x3d5, reg->CRB0, par);
}
- vga_out8 (0x3d4, 0x32, par);
- vga_out8 (0x3d5, par->CR32, par);
+ vga_out8(0x3d4, 0x32, par);
+ vga_out8(0x3d5, reg->CR32, par);
/* unlock extended seq regs */
- vga_out8 (0x3c4, 0x08, par);
- vga_out8 (0x3c5, 0x06, par);
+ vga_out8(0x3c4, 0x08, par);
+ vga_out8(0x3c5, 0x06, par);
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
* that we should leave the default SR10 and SR11 values there.
*/
- if (par->SR10 != 255) {
- vga_out8 (0x3c4, 0x10, par);
- vga_out8 (0x3c5, par->SR10, par);
- vga_out8 (0x3c4, 0x11, par);
- vga_out8 (0x3c5, par->SR11, par);
+ if (reg->SR10 != 255) {
+ vga_out8(0x3c4, 0x10, par);
+ vga_out8(0x3c5, reg->SR10, par);
+ vga_out8(0x3c4, 0x11, par);
+ vga_out8(0x3c5, reg->SR11, par);
}
/* restore extended seq regs for dclk */
- vga_out8 (0x3c4, 0x0e, par);
- vga_out8 (0x3c5, par->SR0E, par);
- vga_out8 (0x3c4, 0x0f, par);
- vga_out8 (0x3c5, par->SR0F, par);
- vga_out8 (0x3c4, 0x12, par);
- vga_out8 (0x3c5, par->SR12, par);
- vga_out8 (0x3c4, 0x13, par);
- vga_out8 (0x3c5, par->SR13, par);
- vga_out8 (0x3c4, 0x29, par);
- vga_out8 (0x3c5, par->SR29, par);
-
- vga_out8 (0x3c4, 0x18, par);
- vga_out8 (0x3c5, par->SR18, par);
+ vga_out8(0x3c4, 0x0e, par);
+ vga_out8(0x3c5, reg->SR0E, par);
+ vga_out8(0x3c4, 0x0f, par);
+ vga_out8(0x3c5, reg->SR0F, par);
+ vga_out8(0x3c4, 0x12, par);
+ vga_out8(0x3c5, reg->SR12, par);
+ vga_out8(0x3c4, 0x13, par);
+ vga_out8(0x3c5, reg->SR13, par);
+ vga_out8(0x3c4, 0x29, par);
+ vga_out8(0x3c5, reg->SR29, par);
+ vga_out8(0x3c4, 0x18, par);
+ vga_out8(0x3c5, reg->SR18, par);
/* load new m, n pll values for dclk & mclk */
- vga_out8 (0x3c4, 0x15, par);
- tmp = vga_in8 (0x3c5, par) & ~0x21;
+ vga_out8(0x3c4, 0x15, par);
+ tmp = vga_in8(0x3c5, par) & ~0x21;
- vga_out8 (0x3c5, tmp | 0x03, par);
- vga_out8 (0x3c5, tmp | 0x23, par);
- vga_out8 (0x3c5, tmp | 0x03, par);
- vga_out8 (0x3c5, par->SR15, par);
- udelay (100);
+ vga_out8(0x3c5, tmp | 0x03, par);
+ vga_out8(0x3c5, tmp | 0x23, par);
+ vga_out8(0x3c5, tmp | 0x03, par);
+ vga_out8(0x3c5, reg->SR15, par);
+ udelay(100);
- vga_out8 (0x3c4, 0x30, par);
- vga_out8 (0x3c5, par->SR30, par);
- vga_out8 (0x3c4, 0x08, par);
- vga_out8 (0x3c5, par->SR08, par);
+ vga_out8(0x3c4, 0x30, par);
+ vga_out8(0x3c5, reg->SR30, par);
+ vga_out8(0x3c4, 0x08, par);
+ vga_out8(0x3c5, reg->SR08, par);
/* now write out cr67 in full, possibly starting STREAMS */
VerticalRetraceWait(par);
- vga_out8 (0x3d4, 0x67, par);
- vga_out8 (0x3d5, par->CR67, par);
+ vga_out8(0x3d4, 0x67, par);
+ vga_out8(0x3d5, reg->CR67, par);
- vga_out8 (0x3d4, 0x66, par);
- cr66 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr66 | 0x80, par);
- vga_out8 (0x3d4, 0x3a, par);
- cr3a = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr3a | 0x80, par);
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x80, par);
+ vga_out8(0x3d4, 0x3a, par);
+ cr3a = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3a | 0x80, par);
if (par->chip != S3_SAVAGE_MX) {
VerticalRetraceWait(par);
- savage_out32 (FIFO_CONTROL_REG, par->MMPR0, par);
- par->SavageWaitIdle (par);
- savage_out32 (MIU_CONTROL_REG, par->MMPR1, par);
- par->SavageWaitIdle (par);
- savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2, par);
- par->SavageWaitIdle (par);
- savage_out32 (MISC_TIMEOUT_REG, par->MMPR3, par);
+ savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
+ par->SavageWaitIdle(par);
+ savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
+ par->SavageWaitIdle(par);
+ savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
+ par->SavageWaitIdle(par);
+ savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
}
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, cr66, par);
- vga_out8 (0x3d4, 0x3a, par);
- vga_out8 (0x3d5, cr3a, par);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66, par);
+ vga_out8(0x3d4, 0x3a, par);
+ vga_out8(0x3d5, cr3a, par);
- SavageSetup2DEngine (par);
- vgaHWProtect (par, 0);
+ SavageSetup2DEngine(par);
+ vgaHWProtect(par, 0);
}
-static void savagefb_update_start (struct savagefb_par *par,
- struct fb_var_screeninfo *var)
+static void savagefb_update_start(struct savagefb_par *par,
+ struct fb_var_screeninfo *var)
{
int base;
/* now program the start address registers */
vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
- vga_out8 (0x3d4, 0x69, par);
- vga_out8 (0x3d5, (base & 0x7f0000) >> 16, par);
+ vga_out8(0x3d4, 0x69, par);
+ vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
}
}
-#if defined(CONFIG_FB_SAVAGE_ACCEL)
-static void savagefb_set_clip(struct fb_info *info)
-{
- struct savagefb_par *par = info->par;
- int cmd;
-
- cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
- par->bci_ptr = 0;
- par->SavageWaitFifo(par,3);
- BCI_SEND(cmd);
- BCI_SEND(BCI_CLIP_TL(0, 0));
- BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
-}
-#endif
-
-static int savagefb_set_par (struct fb_info *info)
+static int savagefb_set_par(struct fb_info *info)
{
struct savagefb_par *par = info->par;
struct fb_var_screeninfo *var = &info->var;
int err;
DBG("savagefb_set_par");
- err = savagefb_decode_var (var, par);
+ err = savagefb_decode_var(var, par, &par->state);
if (err)
return err;
par->maxClock = par->dacSpeedBpp;
par->minClock = 10000;
- savagefb_set_par_int (par);
- fb_set_cmap (&info->cmap, info);
+ savagefb_set_par_int(par, &par->state);
+ fb_set_cmap(&info->cmap, info);
savagefb_set_fix(info);
savagefb_set_clip(info);
/*
* Pan or Wrap the Display
*/
-static int savagefb_pan_display (struct fb_var_screeninfo *var,
- struct fb_info *info)
+static int savagefb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
{
struct savagefb_par *par = info->par;
- savagefb_update_start (par, var);
+ savagefb_update_start(par, var);
return 0;
}
return (blank == FB_BLANK_NORMAL) ? 1 : 0;
}
+static void savagefb_save_state(struct fb_info *info)
+{
+ struct savagefb_par *par = info->par;
+
+ savage_get_default_par(par, &par->save);
+}
+
+static void savagefb_restore_state(struct fb_info *info)
+{
+ struct savagefb_par *par = info->par;
+
+ savagefb_blank(FB_BLANK_POWERDOWN, info);
+ savage_set_default_par(par, &par->save);
+ savagefb_blank(FB_BLANK_UNBLANK, info);
+}
+
static struct fb_ops savagefb_ops = {
.owner = THIS_MODULE,
.fb_check_var = savagefb_check_var,
.fb_setcolreg = savagefb_setcolreg,
.fb_pan_display = savagefb_pan_display,
.fb_blank = savagefb_blank,
+ .fb_save_state = savagefb_save_state,
+ .fb_restore_state = savagefb_restore_state,
#if defined(CONFIG_FB_SAVAGE_ACCEL)
.fb_fillrect = savagefb_fillrect,
.fb_copyarea = savagefb_copyarea,
.vmode = FB_VMODE_NONINTERLACED
};
-static void savage_enable_mmio (struct savagefb_par *par)
+static void savage_enable_mmio(struct savagefb_par *par)
{
unsigned char val;
- DBG ("savage_enable_mmio\n");
+ DBG("savage_enable_mmio\n");
- val = vga_in8 (0x3c3, par);
- vga_out8 (0x3c3, val | 0x01, par);
- val = vga_in8 (0x3cc, par);
- vga_out8 (0x3c2, val | 0x01, par);
+ val = vga_in8(0x3c3, par);
+ vga_out8(0x3c3, val | 0x01, par);
+ val = vga_in8(0x3cc, par);
+ vga_out8(0x3c2, val | 0x01, par);
if (par->chip >= S3_SAVAGE4) {
- vga_out8 (0x3d4, 0x40, par);
- val = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, val | 1, par);
+ vga_out8(0x3d4, 0x40, par);
+ val = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, val | 1, par);
}
}
-static void savage_disable_mmio (struct savagefb_par *par)
+static void savage_disable_mmio(struct savagefb_par *par)
{
unsigned char val;
- DBG ("savage_disable_mmio\n");
+ DBG("savage_disable_mmio\n");
- if(par->chip >= S3_SAVAGE4 ) {
- vga_out8 (0x3d4, 0x40, par);
- val = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, val | 1, par);
+ if (par->chip >= S3_SAVAGE4) {
+ vga_out8(0x3d4, 0x40, par);
+ val = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, val | 1, par);
}
}
-static int __devinit savage_map_mmio (struct fb_info *info)
+static int __devinit savage_map_mmio(struct fb_info *info)
{
struct savagefb_par *par = info->par;
- DBG ("savage_map_mmio");
+ DBG("savage_map_mmio");
- if (S3_SAVAGE3D_SERIES (par->chip))
- par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
+ if (S3_SAVAGE3D_SERIES(par->chip))
+ par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
SAVAGE_NEWMMIO_REGBASE_S3;
else
- par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
+ par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
SAVAGE_NEWMMIO_REGBASE_S4;
par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
- par->mmio.vbase = ioremap (par->mmio.pbase, par->mmio.len);
+ par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
if (!par->mmio.vbase) {
- printk ("savagefb: unable to map memory mapped IO\n");
+ printk("savagefb: unable to map memory mapped IO\n");
return -ENOMEM;
} else
- printk (KERN_INFO "savagefb: mapped io at %p\n",
+ printk(KERN_INFO "savagefb: mapped io at %p\n",
par->mmio.vbase);
info->fix.mmio_start = par->mmio.pbase;
par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
par->bci_ptr = 0;
- savage_enable_mmio (par);
+ savage_enable_mmio(par);
return 0;
}
-static void savage_unmap_mmio (struct fb_info *info)
+static void savage_unmap_mmio(struct fb_info *info)
{
struct savagefb_par *par = info->par;
- DBG ("savage_unmap_mmio");
+ DBG("savage_unmap_mmio");
savage_disable_mmio(par);
}
}
-static int __devinit savage_map_video (struct fb_info *info,
- int video_len)
+static int __devinit savage_map_video(struct fb_info *info,
+ int video_len)
{
struct savagefb_par *par = info->par;
int resource;
DBG("savage_map_video");
- if (S3_SAVAGE3D_SERIES (par->chip))
+ if (S3_SAVAGE3D_SERIES(par->chip))
resource = 0;
else
resource = 1;
- par->video.pbase = pci_resource_start (par->pcidev, resource);
+ par->video.pbase = pci_resource_start(par->pcidev, resource);
par->video.len = video_len;
- par->video.vbase = ioremap (par->video.pbase, par->video.len);
+ par->video.vbase = ioremap(par->video.pbase, par->video.len);
if (!par->video.vbase) {
- printk ("savagefb: unable to map screen memory\n");
+ printk("savagefb: unable to map screen memory\n");
return -ENOMEM;
} else
- printk (KERN_INFO "savagefb: mapped framebuffer at %p, "
- "pbase == %x\n", par->video.vbase, par->video.pbase);
+ printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
+ "pbase == %x\n", par->video.vbase, par->video.pbase);
info->fix.smem_start = par->video.pbase;
info->fix.smem_len = par->video.len - par->cob_size;
info->screen_base = par->video.vbase;
#ifdef CONFIG_MTRR
- par->video.mtrr = mtrr_add (par->video.pbase, video_len,
- MTRR_TYPE_WRCOMB, 1);
+ par->video.mtrr = mtrr_add(par->video.pbase, video_len,
+ MTRR_TYPE_WRCOMB, 1);
#endif
/* Clear framebuffer, it's all white in memory after boot */
- memset_io (par->video.vbase, 0, par->video.len);
+ memset_io(par->video.vbase, 0, par->video.len);
return 0;
}
-static void savage_unmap_video (struct fb_info *info)
+static void savage_unmap_video(struct fb_info *info)
{
struct savagefb_par *par = info->par;
if (par->video.vbase) {
#ifdef CONFIG_MTRR
- mtrr_del (par->video.mtrr, par->video.pbase, par->video.len);
+ mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
#endif
- iounmap (par->video.vbase);
+ iounmap(par->video.vbase);
par->video.vbase = NULL;
info->screen_base = NULL;
}
}
-static int savage_init_hw (struct savagefb_par *par)
+static int savage_init_hw(struct savagefb_par *par)
{
unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
switch (par->chip) {
case S3_SAVAGE3D:
- videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024;
+ videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
break;
case S3_SAVAGE4:
* can do it different...
*/
vga_out8(0x3d4, 0x68, par); /* memory control 1 */
- if( (vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6) )
+ if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
RamSavage4[1] = 8;
/*FALLTHROUGH*/
case S3_SAVAGE2000:
- videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024;
+ videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
break;
case S3_SAVAGE_MX:
case S3_SUPERSAVAGE:
- videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024;
+ videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
break;
case S3_PROSAVAGE:
- videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024;
+ videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
break;
default:
videoRambytes = videoRam * 1024;
- printk (KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
+ printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
/* reset graphics engine to avoid memory corruption */
- vga_out8 (0x3d4, 0x66, par);
- cr66 = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr66 | 0x02, par);
- udelay (10000);
+ vga_out8(0x3d4, 0x66, par);
+ cr66 = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr66 | 0x02, par);
+ udelay(10000);
- vga_out8 (0x3d4, 0x66, par);
- vga_out8 (0x3d5, cr66 & ~0x02, par); /* clear reset flag */
- udelay (10000);
+ vga_out8(0x3d4, 0x66, par);
+ vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
+ udelay(10000);
/*
* reset memory interface, 3D engine, AGP master, PCI master,
* master engine unit, motion compensation/LPB
*/
- vga_out8 (0x3d4, 0x3f, par);
- cr3f = vga_in8 (0x3d5, par);
- vga_out8 (0x3d5, cr3f | 0x08, par);
- udelay (10000);
+ vga_out8(0x3d4, 0x3f, par);
+ cr3f = vga_in8(0x3d5, par);
+ vga_out8(0x3d5, cr3f | 0x08, par);
+ udelay(10000);
- vga_out8 (0x3d4, 0x3f, par);
- vga_out8 (0x3d5, cr3f & ~0x08, par); /* clear reset flags */
- udelay (10000);
+ vga_out8(0x3d4, 0x3f, par);
+ vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
+ udelay(10000);
/* Savage ramdac speeds */
par->numClocks = 4;
n1 = n & 0x1f;
n2 = (n >> 5) & 0x03;
par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
- printk (KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
+ printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
par->MCLK);
/* check for DVI/flat panel */
/* Check LCD panel parrmation */
if (par->display_type == DISP_LCD) {
- unsigned char cr6b = VGArCR( 0x6b, par);
+ unsigned char cr6b = VGArCR(0x6b, par);
- int panelX = (VGArSEQ (0x61, par) +
- ((VGArSEQ (0x66, par) & 0x02) << 7) + 1) * 8;
- int panelY = (VGArSEQ (0x69, par) +
- ((VGArSEQ (0x6e, par) & 0x70) << 4) + 1);
+ int panelX = (VGArSEQ(0x61, par) +
+ ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
+ int panelY = (VGArSEQ(0x69, par) +
+ ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
char * sTechnology = "Unknown";
ActiveDUO = 0x80
};
- if ((VGArSEQ (0x39, par) & 0x03) == 0) {
+ if ((VGArSEQ(0x39, par) & 0x03) == 0) {
sTechnology = "TFT";
- } else if ((VGArSEQ (0x30, par) & 0x01) == 0) {
+ } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
sTechnology = "DSTN";
} else {
sTechnology = "STN";
}
- printk (KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
- panelX, panelY, sTechnology,
- cr6b & ActiveLCD ? "and active" : "but not active");
+ printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
+ panelX, panelY, sTechnology,
+ cr6b & ActiveLCD ? "and active" : "but not active");
- if( cr6b & ActiveLCD ) {
+ if (cr6b & ActiveLCD) {
/*
* If the LCD is active and panel expansion is enabled,
* we probably want to kill the HW cursor.
*/
- printk (KERN_INFO "savagefb: Limiting video mode to "
- "%dx%d\n", panelX, panelY );
+ printk(KERN_INFO "savagefb: Limiting video mode to "
+ "%dx%d\n", panelX, panelY);
par->SavagePanelWidth = panelX;
par->SavagePanelHeight = panelY;
par->display_type = DISP_CRT;
}
- savage_get_default_par (par);
+ savage_get_default_par(par, &par->state);
+ par->save = par->state;
- if( S3_SAVAGE4_SERIES(par->chip) ) {
+ if (S3_SAVAGE4_SERIES(par->chip)) {
/*
* The Savage4 and ProSavage have COB coherency bugs which
* render the buffer useless. We disable it.
return videoRambytes;
}
-static int __devinit savage_init_fb_info (struct fb_info *info,
- struct pci_dev *dev,
- const struct pci_device_id *id)
+static int __devinit savage_init_fb_info(struct fb_info *info,
+ struct pci_dev *dev,
+ const struct pci_device_id *id)
{
struct savagefb_par *par = info->par;
int err = 0;
switch (info->fix.accel) {
case FB_ACCEL_SUPERSAVAGE:
par->chip = S3_SUPERSAVAGE;
- snprintf (info->fix.id, 16, "SuperSavage");
+ snprintf(info->fix.id, 16, "SuperSavage");
break;
case FB_ACCEL_SAVAGE4:
par->chip = S3_SAVAGE4;
- snprintf (info->fix.id, 16, "Savage4");
+ snprintf(info->fix.id, 16, "Savage4");
break;
case FB_ACCEL_SAVAGE3D:
par->chip = S3_SAVAGE3D;
- snprintf (info->fix.id, 16, "Savage3D");
+ snprintf(info->fix.id, 16, "Savage3D");
break;
case FB_ACCEL_SAVAGE3D_MV:
par->chip = S3_SAVAGE3D;
- snprintf (info->fix.id, 16, "Savage3D-MV");
+ snprintf(info->fix.id, 16, "Savage3D-MV");
break;
case FB_ACCEL_SAVAGE2000:
par->chip = S3_SAVAGE2000;
- snprintf (info->fix.id, 16, "Savage2000");
+ snprintf(info->fix.id, 16, "Savage2000");
break;
case FB_ACCEL_SAVAGE_MX_MV:
par->chip = S3_SAVAGE_MX;
- snprintf (info->fix.id, 16, "Savage/MX-MV");
+ snprintf(info->fix.id, 16, "Savage/MX-MV");
break;
case FB_ACCEL_SAVAGE_MX:
par->chip = S3_SAVAGE_MX;
- snprintf (info->fix.id, 16, "Savage/MX");
+ snprintf(info->fix.id, 16, "Savage/MX");
break;
case FB_ACCEL_SAVAGE_IX_MV:
par->chip = S3_SAVAGE_MX;
- snprintf (info->fix.id, 16, "Savage/IX-MV");
+ snprintf(info->fix.id, 16, "Savage/IX-MV");
break;
case FB_ACCEL_SAVAGE_IX:
par->chip = S3_SAVAGE_MX;
- snprintf (info->fix.id, 16, "Savage/IX");
+ snprintf(info->fix.id, 16, "Savage/IX");
break;
case FB_ACCEL_PROSAVAGE_PM:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "ProSavagePM");
+ snprintf(info->fix.id, 16, "ProSavagePM");
break;
case FB_ACCEL_PROSAVAGE_KM:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "ProSavageKM");
+ snprintf(info->fix.id, 16, "ProSavageKM");
break;
case FB_ACCEL_S3TWISTER_P:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "TwisterP");
+ snprintf(info->fix.id, 16, "TwisterP");
break;
case FB_ACCEL_S3TWISTER_K:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "TwisterK");
+ snprintf(info->fix.id, 16, "TwisterK");
break;
case FB_ACCEL_PROSAVAGE_DDR:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "ProSavageDDR");
+ snprintf(info->fix.id, 16, "ProSavageDDR");
break;
case FB_ACCEL_PROSAVAGE_DDRK:
par->chip = S3_PROSAVAGE;
- snprintf (info->fix.id, 16, "ProSavage8");
+ snprintf(info->fix.id, 16, "ProSavage8");
break;
}
info->pixmap.buf_align = 4;
info->pixmap.access_align = 32;
- err = fb_alloc_cmap (&info->cmap, NR_PALETTE, 0);
+ err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
if (!err)
info->flags |= FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT |
/* --------------------------------------------------------------------- */
-static int __devinit savagefb_probe (struct pci_dev* dev,
- const struct pci_device_id* id)
+static int __devinit savagefb_probe(struct pci_dev* dev,
+ const struct pci_device_id* id)
{
struct fb_info *info;
struct savagefb_par *par;
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
- err = register_framebuffer (info);
+ err = register_framebuffer(info);
if (err < 0)
goto failed;
- printk (KERN_INFO "fb: S3 %s frame buffer device\n",
- info->fix.id);
+ printk(KERN_INFO "fb: S3 %s frame buffer device\n",
+ info->fix.id);
/*
* Our driver data
#ifdef CONFIG_FB_SAVAGE_I2C
savagefb_delete_i2c_busses(info);
#endif
- fb_alloc_cmap (&info->cmap, 0, 0);
+ fb_alloc_cmap(&info->cmap, 0, 0);
savage_unmap_video(info);
failed_video:
- savage_unmap_mmio (info);
+ savage_unmap_mmio(info);
failed_mmio:
kfree(info->pixmap.addr);
failed_init:
return err;
}
-static void __devexit savagefb_remove (struct pci_dev *dev)
+static void __devexit savagefb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
* we will be leaving hooks that could cause
* oopsen laying around.
*/
- if (unregister_framebuffer (info))
- printk (KERN_WARNING "savagefb: danger danger! "
- "Oopsen imminent!\n");
+ if (unregister_framebuffer(info))
+ printk(KERN_WARNING "savagefb: danger danger! "
+ "Oopsen imminent!\n");
#ifdef CONFIG_FB_SAVAGE_I2C
savagefb_delete_i2c_busses(info);
#endif
- fb_alloc_cmap (&info->cmap, 0, 0);
- savage_unmap_video (info);
- savage_unmap_mmio (info);
+ fb_alloc_cmap(&info->cmap, 0, 0);
+ savage_unmap_video(info);
+ savage_unmap_mmio(info);
kfree(info->pixmap.addr);
pci_release_regions(dev);
framebuffer_release(info);
}
}
-static int savagefb_suspend (struct pci_dev* dev, pm_message_t state)
+static int savagefb_suspend(struct pci_dev* dev, pm_message_t state)
{
struct fb_info *info = pci_get_drvdata(dev);
struct savagefb_par *par = info->par;
info->fbops->fb_sync(info);
savagefb_blank(FB_BLANK_POWERDOWN, info);
+ savage_set_default_par(par, &par->save);
savage_disable_mmio(par);
pci_save_state(dev);
pci_disable_device(dev);
return 0;
}
-static int savagefb_resume (struct pci_dev* dev)
+static int savagefb_resume(struct pci_dev* dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct savagefb_par *par = info->par;
pci_set_power_state(dev, PCI_D0);
pci_restore_state(dev);
- if(pci_enable_device(dev))
+ if (pci_enable_device(dev))
DBG("err");
pci_set_master(dev);
savage_enable_mmio(par);
savage_init_hw(par);
- savagefb_set_par (info);
+ savagefb_set_par(info);
+ fb_set_suspend(info, 0);
savagefb_blank(FB_BLANK_UNBLANK, info);
- fb_set_suspend (info, 0);
release_console_sem();
return 0;
/* **************************** exit-time only **************************** */
-static void __exit savage_done (void)
+static void __exit savage_done(void)
{
DBG("savage_done");
- pci_unregister_driver (&savagefb_driver);
+ pci_unregister_driver(&savagefb_driver);
}
return -ENODEV;
savagefb_setup(option);
- return pci_register_driver (&savagefb_driver);
+ return pci_register_driver(&savagefb_driver);
}
git.openpandora.org / pandora-kernel.git / blobdiff