/* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
-#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
-#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
+#include <linux/interrupt.h>
#include <asm/io.h>
#include "intelfbhw.h"
struct pll_min_max {
- int min_m, max_m;
- int min_m1, max_m1;
- int min_m2, max_m2;
- int min_n, max_n;
- int min_p, max_p;
- int min_p1, max_p1;
- int min_vco, max_vco;
- int p_transition_clk, ref_clk;
+ int min_m, max_m, min_m1, max_m1;
+ int min_m2, max_m2, min_n, max_n;
+ int min_p, max_p, min_p1, max_p1;
+ int min_vco, max_vco, p_transition_clk, ref_clk;
int p_inc_lo, p_inc_hi;
};
#define PLLS_MAX 2
static struct pll_min_max plls[PLLS_MAX] = {
- { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 48000, 4, 22 }, //I8xx
- { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 96000, 10, 5 } //I9xx
+ { 108, 140, 18, 26,
+ 6, 16, 3, 16,
+ 4, 128, 0, 31,
+ 930000, 1400000, 165000, 48000,
+ 4, 2 }, //I8xx
+
+ { 75, 120, 10, 20,
+ 5, 9, 4, 7,
+ 5, 80, 1, 8,
+ 1400000, 2800000, 200000, 96000,
+ 10, 5 } //I9xx
};
int
{
struct pci_dev *bridge_dev;
u16 tmp;
+ int stolen_overhead;
if (!pdev || !aperture_size || !stolen_size)
return 1;
tmp = 0;
pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
switch (pdev->device) {
- case PCI_DEVICE_ID_INTEL_830M:
- case PCI_DEVICE_ID_INTEL_845G:
+ case PCI_DEVICE_ID_INTEL_915G:
+ case PCI_DEVICE_ID_INTEL_915GM:
+ case PCI_DEVICE_ID_INTEL_945G:
+ case PCI_DEVICE_ID_INTEL_945GM:
+ /* 915 and 945 chipsets support a 256MB aperture.
+ Aperture size is determined by inspected the
+ base address of the aperture. */
+ if (pci_resource_start(pdev, 2) & 0x08000000)
+ *aperture_size = MB(128);
+ else
+ *aperture_size = MB(256);
+ break;
+ default:
if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
*aperture_size = MB(64);
else
*aperture_size = MB(128);
+ break;
+ }
+
+ /* Stolen memory size is reduced by the GTT and the popup.
+ GTT is 1K per MB of aperture size, and popup is 4K. */
+ stolen_overhead = (*aperture_size / MB(1)) + 4;
+ switch(pdev->device) {
+ case PCI_DEVICE_ID_INTEL_830M:
+ case PCI_DEVICE_ID_INTEL_845G:
switch (tmp & INTEL_830_GMCH_GMS_MASK) {
case INTEL_830_GMCH_GMS_STOLEN_512:
- *stolen_size = KB(512) - KB(132);
+ *stolen_size = KB(512) - KB(stolen_overhead);
return 0;
case INTEL_830_GMCH_GMS_STOLEN_1024:
- *stolen_size = MB(1) - KB(132);
+ *stolen_size = MB(1) - KB(stolen_overhead);
return 0;
case INTEL_830_GMCH_GMS_STOLEN_8192:
- *stolen_size = MB(8) - KB(132);
+ *stolen_size = MB(8) - KB(stolen_overhead);
return 0;
case INTEL_830_GMCH_GMS_LOCAL:
ERR_MSG("only local memory found\n");
}
break;
default:
- *aperture_size = MB(128);
switch (tmp & INTEL_855_GMCH_GMS_MASK) {
case INTEL_855_GMCH_GMS_STOLEN_1M:
- *stolen_size = MB(1) - KB(132);
+ *stolen_size = MB(1) - KB(stolen_overhead);
return 0;
case INTEL_855_GMCH_GMS_STOLEN_4M:
- *stolen_size = MB(4) - KB(132);
+ *stolen_size = MB(4) - KB(stolen_overhead);
return 0;
case INTEL_855_GMCH_GMS_STOLEN_8M:
- *stolen_size = MB(8) - KB(132);
+ *stolen_size = MB(8) - KB(stolen_overhead);
return 0;
case INTEL_855_GMCH_GMS_STOLEN_16M:
- *stolen_size = MB(16) - KB(132);
+ *stolen_size = MB(16) - KB(stolen_overhead);
return 0;
case INTEL_855_GMCH_GMS_STOLEN_32M:
- *stolen_size = MB(32) - KB(132);
+ *stolen_size = MB(32) - KB(stolen_overhead);
return 0;
case INTEL_915G_GMCH_GMS_STOLEN_48M:
- *stolen_size = MB(48) - KB(132);
+ *stolen_size = MB(48) - KB(stolen_overhead);
return 0;
case INTEL_915G_GMCH_GMS_STOLEN_64M:
- *stolen_size = MB(64) - KB(132);
+ *stolen_size = MB(64) - KB(stolen_overhead);
return 0;
case INTEL_855_GMCH_GMS_DISABLED:
ERR_MSG("video memory is disabled\n");
offset += dinfo->fb.offset << 12;
- OUTREG(DSPABASE, offset);
+ dinfo->vsync.pan_offset = offset;
+ if ((var->activate & FB_ACTIVATE_VBL) && !intelfbhw_enable_irq(dinfo, 0)) {
+ dinfo->vsync.pan_display = 1;
+ } else {
+ dinfo->vsync.pan_display = 0;
+ OUTREG(DSPABASE, offset);
+ }
return 0;
}
hw->fw_blc_0 = INREG(FW_BLC_0);
hw->fw_blc_1 = INREG(FW_BLC_1);
+ hw->hwstam = INREG16(HWSTAM);
+ hw->ier = INREG16(IER);
+ hw->iir = INREG16(IIR);
+ hw->imr = INREG16(IMR);
+
return 0;
}
static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
{
- int p2_val;
- switch(index)
- {
- case PLLS_I9xx:
- if (p1 == 0)
- return 0;
- if (lvds)
- p2_val = p2 ? 7 : 14;
+ struct pll_min_max *pll = &plls[index];
+ u32 m, vco, p;
+
+ m = (5 * (m1 + 2)) + (m2 + 2);
+ n += 2;
+ vco = pll->ref_clk * m / n;
+
+ if (index == PLLS_I8xx) {
+ p = ((p1 + 2) * (1 << (p2 + 1)));
+ } else {
+ p = ((p1) * (p2 ? 5 : 10));
+ }
+ return vco / p;
+}
+
+#if REGDUMP
+static void
+intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
+{
+ int p1, p2;
+
+ if (IS_I9XX(dinfo)) {
+ if (dpll & DPLL_P1_FORCE_DIV2)
+ p1 = 1;
else
- p2_val = p2 ? 5 : 10;
- return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
- ((p1)) * (p2_val)));
- case PLLS_I8xx:
- default:
- return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
- ((p1+2) * (1 << (p2 + 1)))));
+ p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
+
+ p1 = ffs(p1);
+
+ p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+ } else {
+ if (dpll & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
}
+
+ *o_p1 = p1;
+ *o_p2 = p2;
}
+#endif
+
void
intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
+ intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
+
+ intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (IS_I9XX(dinfo)) {
- int tmpp1;
-
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
-
- tmpp1 = p1;
-
- switch (tmpp1)
- {
- case 0x1: p1 = 1; break;
- case 0x2: p1 = 2; break;
- case 0x4: p1 = 3; break;
- case 0x8: p1 = 4; break;
- case 0x10: p1 = 5; break;
- case 0x20: p1 = 6; break;
- case 0x40: p1 = 7; break;
- case 0x80: p1 = 8; break;
- default: break;
- }
-
- p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
-
- } else {
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
- }
+ intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (IS_I9XX(dinfo)) {
- int tmpp1;
-
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
-
- tmpp1 = p1;
-
- switch (tmpp1)
- {
- case 0x1: p1 = 1; break;
- case 0x2: p1 = 2; break;
- case 0x4: p1 = 3; break;
- case 0x8: p1 = 4; break;
- case 0x10: p1 = 5; break;
- case 0x20: p1 = 6; break;
- case 0x40: p1 = 7; break;
- case 0x80: p1 = 8; break;
- default: break;
- }
-
- p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+ intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
- } else {
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
- }
printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
+ printk(" HWSTAM 0x%04x\n", hw->hwstam);
+ printk(" IER 0x%04x\n", hw->ier);
+ printk(" IIR 0x%04x\n", hw->iir);
+ printk(" IMR 0x%04x\n", hw->imr);
printk("hw state dump end\n");
#endif
}
{
int m1, m2;
int testm;
+ struct pll_min_max *pll = &plls[index];
+
/* no point optimising too much - brute force m */
- for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
- for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
+ for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
+ for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
testm = (5 * (m1 + 2)) + (m2 + 2);
if (testm == m) {
*retm1 = (unsigned int)m1;
splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
{
int p1, p2;
+ struct pll_min_max *pll = &plls[index];
if (index == PLLS_I9xx) {
-
- p2 = 0; // for now
+ p2 = (p % 10) ? 1 : 0;
p1 = p / (p2 ? 5 : 10);
return 0;
}
- if (index == PLLS_I8xx) {
- if (p % 4 == 0)
- p2 = 1;
- else
- p2 = 0;
+ if (p % 4 == 0)
+ p2 = 1;
+ else
+ p2 = 0;
+ p1 = (p / (1 << (p2 + 1))) - 2;
+ if (p % 4 == 0 && p1 < pll->min_p1) {
+ p2 = 0;
p1 = (p / (1 << (p2 + 1))) - 2;
- if (p % 4 == 0 && p1 < plls[index].min_p1) {
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- }
- if (p1 < plls[index].min_p1 ||
- p1 > plls[index].max_p1 ||
- (p1 + 2) * (1 << (p2 + 1)) != p) {
- return 1;
- } else {
- *retp1 = (unsigned int)p1;
- *retp2 = (unsigned int)p2;
- return 0;
- }
}
- return 1;
+ if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
+ (p1 + 2) * (1 << (p2 + 1)) != p) {
+ return 1;
+ } else {
+ *retp1 = (unsigned int)p1;
+ *retp2 = (unsigned int)p2;
+ return 0;
+ }
}
static int
u32 f_vco, p, p_best = 0, m, f_out = 0;
u32 err_max, err_target, err_best = 10000000;
u32 n_best = 0, m_best = 0, f_best, f_err;
- u32 p_min, p_max, p_inc, div_min, div_max;
+ u32 p_min, p_max, p_inc, div_max;
+ struct pll_min_max *pll = &plls[index];
/* Accept 0.5% difference, but aim for 0.1% */
err_max = 5 * clock / 1000;
DBG_MSG("Clock is %d\n", clock);
- div_max = plls[index].max_vco / clock;
- if (index == PLLS_I9xx)
- div_min = 5;
- else
- div_min = ROUND_UP_TO(plls[index].min_vco, clock) / clock;
+ div_max = pll->max_vco / clock;
- if (clock <= plls[index].p_transition_clk)
- p_inc = plls[index].p_inc_lo;
- else
- p_inc = plls[index].p_inc_hi;
- p_min = ROUND_UP_TO(div_min, p_inc);
+ p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
+ p_min = p_inc;
p_max = ROUND_DOWN_TO(div_max, p_inc);
- if (p_min < plls[index].min_p)
- p_min = plls[index].min_p;
- if (p_max > plls[index].max_p)
- p_max = plls[index].max_p;
+ if (p_min < pll->min_p)
+ p_min = pll->min_p;
+ if (p_max > pll->max_p)
+ p_max = pll->max_p;
DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
p += p_inc;
continue;
}
- n = plls[index].min_n;
+ n = pll->min_n;
f_vco = clock * p;
do {
- m = ROUND_UP_TO(f_vco * n, plls[index].ref_clk) / plls[index].ref_clk;
- if (m < plls[index].min_m)
- m = plls[index].min_m + 1;
- if (m > plls[index].max_m)
- m = plls[index].max_m - 1;
+ m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
+ if (m < pll->min_m)
+ m = pll->min_m + 1;
+ if (m > pll->max_m)
+ m = pll->max_m - 1;
for (testm = m - 1; testm <= m; testm++) {
f_out = calc_vclock3(index, m, n, p);
- if (splitm(index, m, &m1, &m2)) {
+ if (splitm(index, testm, &m1, &m2)) {
WRN_MSG("cannot split m = %d\n", m);
n++;
continue;
f_err = f_out - clock + 1;
if (f_err < err_best) {
- m_best = m;
+ m_best = testm;
n_best = n;
p_best = p;
f_best = f_out;
}
}
n++;
- } while ((n <= plls[index].max_n) && (f_out >= clock));
+ } while ((n <= pll->max_n) && (f_out >= clock));
p += p_inc;
} while ((p <= p_max));
u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
u32 vsync_pol, hsync_pol;
u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
+ u32 stride_alignment;
DBG_MSG("intelfbhw_mode_to_hw\n");
*ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
(vactive << SRC_SIZE_VERT_SHIFT);
- hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
+ hw->disp_a_stride = dinfo->pitch;
DBG_MSG("pitch is %d\n", hw->disp_a_stride);
hw->disp_a_base = hw->disp_a_stride * var->yoffset +
hw->disp_a_base += dinfo->fb.offset << 12;
/* Check stride alignment. */
- if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
+ stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
+ STRIDE_ALIGNMENT;
+ if (hw->disp_a_stride % stride_alignment != 0) {
WRN_MSG("display stride %d has bad alignment %d\n",
- hw->disp_a_stride, STRIDE_ALIGNMENT);
+ hw->disp_a_stride, stride_alignment);
return 1;
}
/* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
mdelay(20);
+ OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
+ OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
+ OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
+
/* Disable Sync */
tmp = INREG(ADPA);
tmp &= ~ADPA_DPMS_CONTROL_MASK;
OUTREG(dpll_reg, tmp);
/* Set PLL parameters */
- OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
OUTREG(fp0_reg, *fp0);
OUTREG(fp1_reg, *fp1);
/* Enable PLL */
- tmp = INREG(dpll_reg);
- tmp |= DPLL_VCO_ENABLE;
- OUTREG(dpll_reg, tmp);
+ OUTREG(dpll_reg, *dpll);
/* Set DVOs B/C */
OUTREG(DVOB, hw->dvob);
end = jiffies + (HZ * 3);
while (dinfo->ring_space < n) {
- dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
- RING_HEAD_MASK);
- if (dinfo->ring_tail + RING_MIN_FREE <
- (u32 __iomem) dinfo->ring_head)
- dinfo->ring_space = (u32 __iomem) dinfo->ring_head
+ dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
+ if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
+ dinfo->ring_space = dinfo->ring_head
- (dinfo->ring_tail + RING_MIN_FREE);
else
dinfo->ring_space = (dinfo->ring.size +
- (u32 __iomem) dinfo->ring_head)
+ dinfo->ring_head)
- (dinfo->ring_tail + RING_MIN_FREE);
- if ((u32 __iomem) dinfo->ring_head != last_head) {
+ if (dinfo->ring_head != last_head) {
end = jiffies + (HZ * 3);
- last_head = (u32 __iomem) dinfo->ring_head;
+ last_head = dinfo->ring_head;
}
i++;
if (time_before(end, jiffies)) {
DBG_MSG("refresh_ring\n");
#endif
- dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
- RING_HEAD_MASK);
+ dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
- if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
- dinfo->ring_space = (u32 __iomem) dinfo->ring_head
+ if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
+ dinfo->ring_space = dinfo->ring_head
- (dinfo->ring_tail + RING_MIN_FREE);
else
- dinfo->ring_space = (dinfo->ring.size +
- (u32 __iomem) dinfo->ring_head)
+ dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
- (dinfo->ring_tail + RING_MIN_FREE);
}
addr += 16;
}
}
+
+static irqreturn_t
+intelfbhw_irq(int irq, void *dev_id, struct pt_regs *fp) {
+ int handled = 0;
+ u16 tmp;
+ struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
+
+ spin_lock(&dinfo->int_lock);
+
+ tmp = INREG16(IIR);
+ tmp &= VSYNC_PIPE_A_INTERRUPT;
+
+ if (tmp == 0) {
+ spin_unlock(&dinfo->int_lock);
+ return IRQ_RETVAL(handled);
+ }
+
+ OUTREG16(IIR, tmp);
+
+ if (tmp & VSYNC_PIPE_A_INTERRUPT) {
+ dinfo->vsync.count++;
+ if (dinfo->vsync.pan_display) {
+ dinfo->vsync.pan_display = 0;
+ OUTREG(DSPABASE, dinfo->vsync.pan_offset);
+ }
+ wake_up_interruptible(&dinfo->vsync.wait);
+ handled = 1;
+ }
+
+ spin_unlock(&dinfo->int_lock);
+
+ return IRQ_RETVAL(handled);
+}
+
+int
+intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
+
+ if (!test_and_set_bit(0, &dinfo->irq_flags)) {
+ if (request_irq(dinfo->pdev->irq, intelfbhw_irq, SA_SHIRQ, "intelfb", dinfo)) {
+ clear_bit(0, &dinfo->irq_flags);
+ return -EINVAL;
+ }
+
+ spin_lock_irq(&dinfo->int_lock);
+ OUTREG16(HWSTAM, 0xfffe);
+ OUTREG16(IMR, 0x0);
+ OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
+ spin_unlock_irq(&dinfo->int_lock);
+ } else if (reenable) {
+ u16 ier;
+
+ spin_lock_irq(&dinfo->int_lock);
+ ier = INREG16(IER);
+ if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
+ DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
+ OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
+ }
+ spin_unlock_irq(&dinfo->int_lock);
+ }
+ return 0;
+}
+
+void
+intelfbhw_disable_irq(struct intelfb_info *dinfo) {
+ u16 tmp;
+
+ if (test_and_clear_bit(0, &dinfo->irq_flags)) {
+ if (dinfo->vsync.pan_display) {
+ dinfo->vsync.pan_display = 0;
+ OUTREG(DSPABASE, dinfo->vsync.pan_offset);
+ }
+ spin_lock_irq(&dinfo->int_lock);
+ OUTREG16(HWSTAM, 0xffff);
+ OUTREG16(IMR, 0xffff);
+ OUTREG16(IER, 0x0);
+
+ tmp = INREG16(IIR);
+ OUTREG16(IIR, tmp);
+ spin_unlock_irq(&dinfo->int_lock);
+
+ free_irq(dinfo->pdev->irq, dinfo);
+ }
+}
+
+int
+intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) {
+ struct intelfb_vsync *vsync;
+ unsigned int count;
+ int ret;
+
+ switch (pipe) {
+ case 0:
+ vsync = &dinfo->vsync;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ ret = intelfbhw_enable_irq(dinfo, 0);
+ if (ret) {
+ return ret;
+ }
+
+ count = vsync->count;
+ ret = wait_event_interruptible_timeout(vsync->wait, count != vsync->count, HZ/10);
+ if (ret < 0) {
+ return ret;
+ }
+ if (ret == 0) {
+ intelfbhw_enable_irq(dinfo, 1);
+ DBG_MSG("wait_for_vsync timed out!\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
git.openpandora.org / pandora-kernel.git / blobdiff