usb/xhci: move xhci_gen_setup() away from -pci.

[pandora-kernel.git] / drivers / usb / host / xhci.c

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index a8c3e8a..2409bbe 100644 (file)
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -3944,6 +3944,95 @@ int xhci_get_frame(struct usb_hcd *hcd)
        return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
 }
 
+int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+{
+       struct xhci_hcd         *xhci;
+       struct device           *dev = hcd->self.controller;
+       int                     retval;
+       u32                     temp;
+
+       hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
+
+       if (usb_hcd_is_primary_hcd(hcd)) {
+               xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
+               if (!xhci)
+                       return -ENOMEM;
+               *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
+               xhci->main_hcd = hcd;
+               /* Mark the first roothub as being USB 2.0.
+                * The xHCI driver will register the USB 3.0 roothub.
+                */
+               hcd->speed = HCD_USB2;
+               hcd->self.root_hub->speed = USB_SPEED_HIGH;
+               /*
+                * USB 2.0 roothub under xHCI has an integrated TT,
+                * (rate matching hub) as opposed to having an OHCI/UHCI
+                * companion controller.
+                */
+               hcd->has_tt = 1;
+       } else {
+               /* xHCI private pointer was set in xhci_pci_probe for the second
+                * registered roothub.
+                */
+               xhci = hcd_to_xhci(hcd);
+               temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+               if (HCC_64BIT_ADDR(temp)) {
+                       xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+                       dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
+               } else {
+                       dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
+               }
+               return 0;
+       }
+
+       xhci->cap_regs = hcd->regs;
+       xhci->op_regs = hcd->regs +
+               HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
+       xhci->run_regs = hcd->regs +
+               (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
+       /* Cache read-only capability registers */
+       xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
+       xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
+       xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
+       xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
+       xhci->hci_version = HC_VERSION(xhci->hcc_params);
+       xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+       xhci_print_registers(xhci);
+
+       get_quirks(dev, xhci);
+
+       /* Make sure the HC is halted. */
+       retval = xhci_halt(xhci);
+       if (retval)
+               goto error;
+
+       xhci_dbg(xhci, "Resetting HCD\n");
+       /* Reset the internal HC memory state and registers. */
+       retval = xhci_reset(xhci);
+       if (retval)
+               goto error;
+       xhci_dbg(xhci, "Reset complete\n");
+
+       temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+       if (HCC_64BIT_ADDR(temp)) {
+               xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+               dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
+       } else {
+               dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
+       }
+
+       xhci_dbg(xhci, "Calling HCD init\n");
+       /* Initialize HCD and host controller data structures. */
+       retval = xhci_init(hcd);
+       if (retval)
+               goto error;
+       xhci_dbg(xhci, "Called HCD init\n");
+       return 0;
+error:
+       kfree(xhci);
+       return retval;
+}
+
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_LICENSE("GPL");