Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[pandora-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index b7eb793..e99e319 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -673,7 +673,7 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
        REGWRITE_BUFFER_FLUSH(ah);
 }
 
-unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
+u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
 {
        REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
        udelay(100);
@@ -686,7 +686,6 @@ unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
 
-#define DPLL3_PHASE_SHIFT_VAL 0x1
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                              struct ath9k_channel *chan)
 {
@@ -723,9 +722,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
                              AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
                udelay(1000);
-
-               REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
-                             AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
        } else if (AR_SREV_9340(ah)) {
                u32 regval, pll2_divint, pll2_divfrac, refdiv;
 
@@ -1324,15 +1320,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
        ah->txchainmask = common->tx_chainmask;
        ah->rxchainmask = common->rx_chainmask;
 
-       if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
-               ath9k_hw_abortpcurecv(ah);
-               if (!ath9k_hw_stopdmarecv(ah)) {
-                       ath_dbg(common, ATH_DBG_XMIT,
-                               "Failed to stop receive dma\n");
-                       bChannelChange = false;
-               }
-       }
-
        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                return -EIO;
 
@@ -1866,7 +1853,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
        struct ath_common *common = ath9k_hw_common(ah);
        struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
-       u16 capField = 0, eeval;
+       u16 eeval;
        u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
 
        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
@@ -1877,8 +1864,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                eeval |= AR9285_RDEXT_DEFAULT;
        regulatory->current_rd_ext = eeval;
 
-       capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
-
        if (ah->opmode != NL80211_IFTYPE_AP &&
            ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
                if (regulatory->current_rd == 0x64 ||
@@ -2432,11 +2417,11 @@ EXPORT_SYMBOL(ath_gen_timer_alloc);
 
 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
                              struct ath_gen_timer *timer,
-                             u32 timer_next,
+                             u32 trig_timeout,
                              u32 timer_period)
 {
        struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
-       u32 tsf;
+       u32 tsf, timer_next;
 
        BUG_ON(!timer_period);
 
@@ -2444,17 +2429,12 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 
        tsf = ath9k_hw_gettsf32(ah);
 
+       timer_next = tsf + trig_timeout;
+
        ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
                "current tsf %x period %x timer_next %x\n",
                tsf, timer_period, timer_next);
 
-       /*
-        * Pull timer_next forward if the current TSF already passed it
-        * because of software latency
-        */
-       if (timer_next < tsf)
-               timer_next = tsf + timer_period;
-
        /*
         * Program generic timer registers
         */