Merge branch 'core-rcu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[pandora-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
index 892c48b..1baca8e 100644 (file)
@@ -75,7 +75,19 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
        freq = centers.synth_center;
 
        if (freq < 4800) {     /* 2 GHz, fractional mode */
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah)) {
+                       u32 chan_frac;
+                       u32 div;
+
+                       if (ah->is_clk_25mhz)
+                               div = 75;
+                       else
+                               div = 120;
+
+                       channelSel = (freq * 4) / div;
+                       chan_frac = (((freq * 4) % div) * 0x20000) / div;
+                       channelSel = (channelSel << 17) | chan_frac;
+               } else if (AR_SREV_9485(ah)) {
                        u32 chan_frac;
 
                        /*
@@ -104,7 +116,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                        u32 chan_frac;
 
                        channelSel = (freq * 2) / 75;
-                       chan_frac = ((freq % 75) * 0x20000) / 75;
+                       chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
                        channelSel = (channelSel << 17) | chan_frac;
                } else {
                        channelSel = CHANSEL_5G(freq);
@@ -168,7 +180,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
         * is out-of-band and can be ignored.
         */
 
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
+       if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
                                                         IS_CHAN_2GHZ(chan));
                if (spur_fbin_ptr[0] == 0) /* No spur */
@@ -193,7 +205,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 
        for (i = 0; i < max_spur_cnts; i++) {
                negative = 0;
-               if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+               if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
                                        IS_CHAN_2GHZ(chan)) - synth_freq;
                else
@@ -659,6 +671,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                modesIndex, regWrites);
 
+       if (AR_SREV_9300(ah))
+               REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
+
        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 
@@ -1074,7 +1089,10 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
 {
        ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
        ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
-       ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
+       if (AR_SREV_9330(ah))
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
+       else
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
        ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
        ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
        ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
@@ -1196,8 +1214,17 @@ static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
-       antconf->lna1_lna2_delta = -9;
-       antconf->div_group = 2;
+
+       if (AR_SREV_9330_11(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 1;
+       } else if (AR_SREV_9485(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 2;
+       } else {
+               antconf->lna1_lna2_delta = -3;
+               antconf->div_group = 0;
+       }
 }
 
 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,