Merge branch 'i2c-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvar...

[pandora-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index ff8150e..d109c25 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -14,6 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include <asm/unaligned.h>
 #include "hw.h"
 #include "ar9003_phy.h"
 #include "ar9003_eeprom.h"
@@ -1461,7 +1462,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-               { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+               { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
@@ -2616,7 +2617,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
@@ -3006,11 +3007,11 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
 
        switch (param) {
        case EEP_MAC_LSW:
-               return eep->macAddr[0] << 8 | eep->macAddr[1];
+               return get_unaligned_be16(eep->macAddr);
        case EEP_MAC_MID:
-               return eep->macAddr[2] << 8 | eep->macAddr[3];
+               return get_unaligned_be16(eep->macAddr + 2);
        case EEP_MAC_MSW:
-               return eep->macAddr[4] << 8 | eep->macAddr[5];
+               return get_unaligned_be16(eep->macAddr + 4);
        case EEP_REG_0:
                return le16_to_cpu(pBase->regDmn[0]);
        case EEP_REG_1:
@@ -3038,7 +3039,7 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
        case EEP_CHAIN_MASK_REDUCE:
                return (pBase->miscConfiguration >> 0x3) & 0x1;
        case EEP_ANT_DIV_CTL1:
-               return le32_to_cpu(eep->base_ext1.ant_div_control);
+               return eep->base_ext1.ant_div_control;
        default:
                return 0;
        }
@@ -3324,6 +3325,8 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
        read = ar9300_read_eeprom;
        if (AR_SREV_9485(ah))
                cptr = AR9300_BASE_ADDR_4K;
+       else if (AR_SREV_9330(ah))
+               cptr = AR9300_BASE_ADDR_512;
        else
                cptr = AR9300_BASE_ADDR;
        ath_dbg(common, ATH_DBG_EEPROM,
@@ -3378,8 +3381,7 @@ found:
                osize = length;
                read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
-               mchecksum = word[COMP_HDR_LEN + osize] |
-                   (word[COMP_HDR_LEN + osize + 1] << 8);
+               mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
                ath_dbg(common, ATH_DBG_EEPROM,
                        "checksum %x %x\n", checksum, mchecksum);
                if (checksum == mchecksum) {
@@ -3442,7 +3444,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
 
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
        else {
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3523,7 +3525,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                }
        }
 
-       if (AR_SREV_9485(ah)) {
+       if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /*
                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
@@ -3710,7 +3712,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 
        if (internal_regulator) {
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                        int reg_pmu_set;
 
                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
@@ -3718,9 +3720,24 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
                                return;
 
-                       reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
-                                     (2 << 14) | (6 << 17) | (1 << 20) |
-                                     (3 << 24) | (1 << 28);
+                       if (AR_SREV_9330(ah)) {
+                               if (ah->is_clk_25mhz) {
+                                       reg_pmu_set = (3 << 1) | (8 << 4) |
+                                                     (3 << 8) | (1 << 14) |
+                                                     (6 << 17) | (1 << 20) |
+                                                     (3 << 24);
+                               } else {
+                                       reg_pmu_set = (4 << 1)  | (7 << 4) |
+                                                     (3 << 8)  | (1 << 14) |
+                                                     (6 << 17) | (1 << 20) |
+                                                     (3 << 24);
+                               }
+                       } else {
+                               reg_pmu_set = (5 << 1) | (7 << 4) |
+                                             (1 << 8) | (2 << 14) |
+                                             (6 << 17) | (1 << 20) |
+                                             (3 << 24) | (1 << 28);
+                       }
 
                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
@@ -3751,7 +3768,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
                }
        } else {
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
                                              AR_PHY_PMU2_PGM))
@@ -3795,9 +3812,9 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
        ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
        ar9003_hw_drive_strength_apply(ah);
        ar9003_hw_atten_apply(ah, chan);
-       if (!AR_SREV_9340(ah))
+       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
                ar9003_hw_internal_regulator_apply(ah);
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
                ar9003_hw_apply_tuning_caps(ah);
 }