Merge branch 'misc' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc...

[pandora-kernel.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 7f4b7f6..8c8b987 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -138,6 +138,8 @@
 #define   ASIC_REV_5752                         0x06
 #define   ASIC_REV_5780                         0x08
 #define   ASIC_REV_5714                         0x09
+#define   ASIC_REV_5755                         0x0a
+#define   ASIC_REV_5787                         0x0b
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -455,6 +457,7 @@
 #define  RX_MODE_PROMISC                0x00000100
 #define  RX_MODE_NO_CRC_CHECK           0x00000200
 #define  RX_MODE_KEEP_VLAN_TAG          0x00000400
+#define  RX_MODE_IPV6_CSUM_ENABLE       0x01000000
 #define MAC_RX_STATUS                  0x0000046c
 #define  RX_STATUS_REMOTE_TX_XOFFED     0x00000001
 #define  RX_STATUS_XOFF_RCVD            0x00000002
@@ -1339,6 +1342,7 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_GPIO_UART_SEL     0x00000010      /* 5755 only */
 #define  GRC_LCLCTRL_USE_SIG_DETECT    0x00000010      /* 5714/5780 only */
 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT        0x00000020      /* 5714/5780 only */
 #define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
@@ -1393,6 +1397,7 @@
 #define GRC_MDI_CTRL                   0x00006844
 #define GRC_SEEPROM_DELAY              0x00006848
 /* 0x684c --> 0x6c00 unused */
+#define GRC_FASTBOOT_PC                        0x00006894      /* 5752, 5755, 5787 */
 
 /* 0x6c00 --> 0x7000 unused */
 
@@ -1436,6 +1441,16 @@
 #define  FLASH_5752VENDOR_ST_M45PE10    0x02400000
 #define  FLASH_5752VENDOR_ST_M45PE20    0x02400002
 #define  FLASH_5752VENDOR_ST_M45PE40    0x02400001
+#define  FLASH_5755VENDOR_ATMEL_FLASH_1         0x03400001
+#define  FLASH_5755VENDOR_ATMEL_FLASH_2         0x03400002
+#define  FLASH_5755VENDOR_ATMEL_FLASH_3         0x03400000
+#define  FLASH_5755VENDOR_ATMEL_FLASH_4         0x00000003
+#define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ    0x03c00003
+#define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ   0x03c00002
+#define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ    0x03000003
+#define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ   0x03000002
+#define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ    0x03000000
+#define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ   0x02000000
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
 #define  FLASH_5752PAGE_SIZE_256        0x00000000
 #define  FLASH_5752PAGE_SIZE_512        0x10000000
@@ -2156,13 +2171,13 @@ struct tg3 {
 #define TG3_FLAG_PCIX_MODE             0x00020000
 #define TG3_FLAG_PCI_HIGH_SPEED                0x00040000
 #define TG3_FLAG_PCI_32BIT             0x00080000
-#define TG3_FLAG_NO_TX_PSEUDO_CSUM     0x00100000
-#define TG3_FLAG_NO_RX_PSEUDO_CSUM     0x00200000
+#define TG3_FLAG_SRAM_USE_CONFIG       0x00100000
 #define TG3_FLAG_SERDES_WOL_CAP                0x00400000
 #define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_IN_RESET_TASK         0x04000000
+#define TG3_FLAG_40BIT_DMA_BUG         0x08000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
 #define TG3_FLAG_GOT_SERDES_FLOWCTL    0x20000000
 #define TG3_FLAG_SPLIT_MODE            0x40000000
@@ -2184,7 +2199,7 @@ struct tg3 {
 #define TG3_FLG2_PHY_SERDES            0x00002000
 #define TG3_FLG2_CAPACITIVE_COUPLING   0x00004000
 #define TG3_FLG2_FLASH                 0x00008000
-#define TG3_FLG2_HW_TSO                        0x00010000
+#define TG3_FLG2_HW_TSO_1              0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
 #define TG3_FLG2_5705_PLUS             0x00040000
 #define TG3_FLG2_5750_PLUS             0x00080000
@@ -2197,6 +2212,9 @@ struct tg3 {
 #define TG3_FLG2_PARALLEL_DETECT       0x01000000
 #define TG3_FLG2_ICH_WORKAROUND                0x02000000
 #define TG3_FLG2_5780_CLASS            0x04000000
+#define TG3_FLG2_HW_TSO_2              0x08000000
+#define TG3_FLG2_HW_TSO                        (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
+#define TG3_FLG2_1SHOT_MSI             0x10000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2246,6 +2264,8 @@ struct tg3 {
 #define PHY_ID_BCM5752                 0x60008100
 #define PHY_ID_BCM5714                 0x60008340
 #define PHY_ID_BCM5780                 0x60008350
+#define PHY_ID_BCM5755                 0xbc050cc0
+#define PHY_ID_BCM5787                 0xbc050ce0
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
 #define PHY_ID_REV_MASK                        0x0000000f
@@ -2257,6 +2277,7 @@ struct tg3 {
        u32                             led_ctrl;
 
        char                            board_part_number[24];
+       char                            fw_ver[16];
        u32                             nic_sram_data_cfg;
        u32                             pci_clock_ctrl;
        struct pci_dev                  *pdev_peer;
@@ -2270,7 +2291,8 @@ struct tg3 {
         (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
         (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
         (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
-        (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)
+        (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
+        (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
 
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;