mlx4_core: Support ICM tables in coherent memory

[pandora-kernel.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index dcdfc08..5c21f49 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1150,6 +1150,9 @@
 #define  VCPU_STATUS_INIT_DONE          0x04000000
 #define  VCPU_STATUS_DRV_RESET          0x08000000
 
+#define VCPU_CFGSHDW                   0x00005104
+#define  VCPU_CFGSHDW_ASPM_DBNC                 0x00001000
+
 /* Mailboxes */
 #define GRCMBOX_BASE                   0x00005600
 #define GRCMBOX_INTERRUPT_0            0x00005800 /* 64-bit */
@@ -1464,6 +1467,7 @@
 #define  FLASH_5755VENDOR_ATMEL_FLASH_2         0x03400002
 #define  FLASH_5755VENDOR_ATMEL_FLASH_3         0x03400000
 #define  FLASH_5755VENDOR_ATMEL_FLASH_4         0x00000003
+#define  FLASH_5755VENDOR_ATMEL_FLASH_5         0x02000003
 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ    0x03c00003
 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ   0x03c00002
 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ    0x03000003
@@ -1507,6 +1511,8 @@
 #define PCIE_TRANS_CFG_1SHOT_MSI        0x20000000
 #define PCIE_TRANS_CFG_LOM              0x00000020
 
+#define PCIE_PWR_MGMT_THRESH           0x00007d28
+#define PCIE_PWR_MGMT_L1_THRESH_MSK     0x0000ff00
 
 #define TG3_EEPROM_MAGIC               0x669955aa
 #define TG3_EEPROM_MAGIC_FW            0xa5000000
@@ -1593,6 +1599,9 @@
 #define  SHASTA_EXT_LED_MAC             0x00010000
 #define  SHASTA_EXT_LED_COMBO           0x00018000
 
+#define NIC_SRAM_DATA_CFG_3            0x00000d3c
+#define  NIC_SRAM_ASPM_DEBOUNCE                 0x00000002
+
 #define NIC_SRAM_RX_MINI_BUFFER_DESC   0x00001000
 
 #define NIC_SRAM_DMA_DESC_POOL_BASE    0x00002000
@@ -1634,6 +1643,11 @@
 
 #define MII_TG3_AUX_CTRL               0x18 /* auxilliary control register */
 
+#define MII_TG3_AUXCTL_MISC_WREN       0x8000
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX        0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISC            0x0007
+
 #define MII_TG3_AUX_STAT               0x19 /* auxilliary status register */
 #define MII_TG3_AUX_STAT_LPASS         0x0004
 #define MII_TG3_AUX_STAT_SPDMASK       0x0700
@@ -1659,6 +1673,9 @@
 #define MII_TG3_EPHY_TEST              0x1f /* 5906 PHY register */
 #define MII_TG3_EPHY_SHADOW_EN         0x80
 
+#define MII_TG3_EPHYTST_MISCCTRL       0x10 /* 5906 EPHY misc ctrl shadow register */
+#define MII_TG3_EPHYTST_MISCCTRL_MDIX  0x4000
+
 #define MII_TG3_TEST1                  0x1e
 #define MII_TG3_TEST1_TRIM_EN          0x0010
 #define MII_TG3_TEST1_CRC_EN           0x8000
@@ -2200,6 +2217,7 @@ struct tg3 {
 #define TG3_FLAG_USE_LINKCHG_REG       0x00000008
 #define TG3_FLAG_USE_MI_INTERRUPT      0x00000010
 #define TG3_FLAG_ENABLE_ASF            0x00000020
+#define TG3_FLAG_ASPM_WORKAROUND       0x00000040
 #define TG3_FLAG_POLL_SERDES           0x00000080
 #define TG3_FLAG_MBOX_WRITE_REORDER    0x00000100
 #define TG3_FLAG_PCIX_TARGET_HWBUG     0x00000200
@@ -2219,7 +2237,7 @@ struct tg3 {
 #define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
-#define TG3_FLAG_IN_RESET_TASK         0x04000000
+
 #define TG3_FLAG_40BIT_DMA_BUG         0x08000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
 #define TG3_FLAG_SUPPORT_MSI           0x20000000
@@ -2288,6 +2306,7 @@ struct tg3 {
        u32                             grc_local_ctrl;
        u32                             dma_rwctrl;
        u32                             coalesce_mode;
+       u32                             pwrmgmt_thresh;
 
        /* PCI block */
        u16                             pci_chip_rev_id;
@@ -2326,6 +2345,7 @@ struct tg3 {
 #define PHY_REV_BCM5411_X0             0x1 /* Found on Netgear GA302T */
 
        u32                             led_ctrl;
+       u32                             pci_cmd;
 
        char                            board_part_number[24];
        char                            fw_ver[16];