Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

[pandora-kernel.git] / drivers / net / smc91x.h

diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 69e97a1..22209b6 100644 (file)
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -40,23 +40,46 @@
  * Define your architecture specific bus configuration parameters here.
  */
 
-#if    defined(CONFIG_ARCH_LUBBOCK)
+#if defined(CONFIG_ARCH_LUBBOCK) ||\
+    defined(CONFIG_MACH_MAINSTONE) ||\
+    defined(CONFIG_MACH_ZYLONITE) ||\
+    defined(CONFIG_MACH_LITTLETON)
 
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT       0
+#include <asm/mach-types.h>
+
+/* Now the bus width is specified in the platform data
+ * pretend here to support all I/O access types
+ */
+#define SMC_CAN_USE_8BIT       1
 #define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      0
+#define SMC_CAN_USE_32BIT      1
 #define SMC_NOWAIT             1
 
-/* The first two address lines aren't connected... */
-#define SMC_IO_SHIFT           2
+#define SMC_IO_SHIFT           (lp->io_shift)
 
+#define SMC_inb(a, r)          readb((a) + (r))
 #define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
+#define SMC_inl(a, r)          readl((a) + (r))
+#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
+#define SMC_outl(v, a, r)      writel(v, (a) + (r))
 #define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
+#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
 #define SMC_IRQ_FLAGS          (-1)    /* from resource */
 
+/* We actually can't write halfwords properly if not word aligned */
+static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
+{
+       if (machine_is_mainstone() && reg & 2) {
+               unsigned int v = val << 16;
+               v |= readl(ioaddr + (reg & ~2)) & 0xffff;
+               writel(v, ioaddr + (reg & ~2));
+       } else {
+               writew(val, ioaddr + reg);
+       }
+}
+
 #elif defined(CONFIG_BLACKFIN)
 
 #define SMC_IRQ_FLAGS          IRQF_TRIGGER_HIGH
@@ -93,14 +116,14 @@
 #define SMC_insw(a, r, p, l)   insw ((unsigned long *)((a) + (r)), p, l)
 # endif
 /* check if the mac in reg is valid */
-#define SMC_GET_MAC_ADDR(addr)                                 \
+#define SMC_GET_MAC_ADDR(lp, addr)                             \
        do {                                                    \
                unsigned int __v;                               \
-               __v = SMC_inw(ioaddr, ADDR0_REG);               \
+               __v = SMC_inw(ioaddr, ADDR0_REG(lp));           \
                addr[0] = __v; addr[1] = __v >> 8;              \
-               __v = SMC_inw(ioaddr, ADDR1_REG);               \
+               __v = SMC_inw(ioaddr, ADDR1_REG(lp));           \
                addr[2] = __v; addr[3] = __v >> 8;              \
-               __v = SMC_inw(ioaddr, ADDR2_REG);               \
+               __v = SMC_inw(ioaddr, ADDR2_REG(lp));           \
                addr[4] = __v; addr[5] = __v >> 8;              \
                if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) {         \
                        random_ether_addr(addr);                \
@@ -195,7 +218,6 @@
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
 
 #elif  defined(CONFIG_ARCH_INNOKOM) || \
-       defined(CONFIG_MACH_MAINSTONE) || \
        defined(CONFIG_ARCH_PXA_IDP) || \
        defined(CONFIG_ARCH_RAMSES) || \
        defined(CONFIG_ARCH_PCM027)
@@ -229,22 +251,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
        }
 }
 
-#elif defined(CONFIG_MACH_ZYLONITE)
-
-#define SMC_CAN_USE_8BIT        1
-#define SMC_CAN_USE_16BIT       1
-#define SMC_CAN_USE_32BIT       0
-#define SMC_IO_SHIFT            0
-#define SMC_NOWAIT              1
-#define SMC_USE_PXA_DMA                1
-#define SMC_inb(a, r)           readb((a) + (r))
-#define SMC_inw(a, r)           readw((a) + (r))
-#define SMC_insw(a, r, p, l)    insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l)   outsw((a) + (r), p, l)
-#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)       writew(v, (a) + (r))
-#define SMC_IRQ_FLAGS          (-1)    /* from resource */
-
 #elif  defined(CONFIG_ARCH_OMAP)
 
 /* We can only do 16-bit reads and writes in the static memory space. */
@@ -454,7 +460,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 #define RPC_LSA_DEFAULT                RPC_LED_100_10
 #define RPC_LSB_DEFAULT                RPC_LED_TX_RX
 
-#define SMC_DYNAMIC_BUS_CONFIG
 #endif
 
 
@@ -493,7 +498,7 @@ struct smc_local {
 
        spinlock_t lock;
 
-#ifdef SMC_USE_PXA_DMA
+#ifdef CONFIG_ARCH_PXA
        /* DMA needs the physical address of the chip */
        u_long physaddr;
        struct device *device;
@@ -501,20 +506,17 @@ struct smc_local {
        void __iomem *base;
        void __iomem *datacs;
 
+       /* the low address lines on some platforms aren't connected... */
+       int     io_shift;
+
        struct smc91x_platdata cfg;
 };
 
-#ifdef SMC_DYNAMIC_BUS_CONFIG
-#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
-#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
-#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
-#else
-#define SMC_8BIT(p) SMC_CAN_USE_8BIT
-#define SMC_16BIT(p) SMC_CAN_USE_16BIT
-#define SMC_32BIT(p) SMC_CAN_USE_32BIT
-#endif
+#define SMC_8BIT(p)    ((p)->cfg.flags & SMC91X_USE_8BIT)
+#define SMC_16BIT(p)   ((p)->cfg.flags & SMC91X_USE_16BIT)
+#define SMC_32BIT(p)   ((p)->cfg.flags & SMC91X_USE_32BIT)
 
-#ifdef SMC_USE_PXA_DMA
+#ifdef CONFIG_ARCH_PXA
 /*
  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
  * always happening in irq context so no need to worry about races.  TX is
@@ -608,7 +610,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 {
        DCSR(dma) = 0;
 }
-#endif  /* SMC_USE_PXA_DMA */
+#endif  /* CONFIG_ARCH_PXA */
 
 
 /*