/*******************************************************************************
Intel PRO/1000 Linux driver
- Copyright(c) 1999 - 2008 Intel Corporation.
+ Copyright(c) 1999 - 2009 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
* 82578DC Gigabit Network Connection
*/
-#include <linux/netdevice.h>
-#include <linux/ethtool.h>
-#include <linux/delay.h>
-#include <linux/pci.h>
-
#include "e1000.h"
#define ICH_FLASH_GFPREG 0x0000
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
-static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
{
phy->reset_delay_us = 100;
phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
- phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
- phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
+ phy->ops.read_reg = e1000_read_phy_reg_hv;
+ phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
- phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
- phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
+ phy->ops.write_reg = e1000_write_phy_reg_hv;
+ phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->id = e1000_phy_unknown;
phy->ops.force_speed_duplex =
e1000_phy_force_speed_duplex_82577;
phy->ops.get_cable_length = e1000_get_cable_length_82577;
- phy->ops.get_phy_info = e1000_get_phy_info_82577;
- phy->ops.commit_phy = e1000e_phy_sw_reset;
+ phy->ops.get_info = e1000_get_phy_info_82577;
+ phy->ops.commit = e1000e_phy_sw_reset;
}
return ret_val;
*/
ret_val = e1000e_determine_phy_address(hw);
if (ret_val) {
- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
ret_val = e1000e_determine_phy_address(hw);
if (ret_val)
return ret_val;
case IGP03E1000_E_PHY_ID:
phy->type = e1000_phy_igp_3;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
- phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
+ phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
+ phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
break;
case IFE_E_PHY_ID:
case IFE_PLUS_E_PHY_ID:
case BME1000_E_PHY_ID:
phy->type = e1000_phy_bm;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
- hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
+ phy->ops.commit = e1000e_phy_sw_reset;
break;
default:
return -E1000_ERR_PHY;
/* Can't read flash registers if the register set isn't mapped. */
if (!hw->flash_address) {
- hw_dbg(hw, "ERROR: Flash registers not mapped\n");
+ e_dbg("ERROR: Flash registers not mapped\n");
return -E1000_ERR_CONFIG;
}
/* Clear shadow ram */
for (i = 0; i < nvm->word_size; i++) {
- dev_spec->shadow_ram[i].modified = 0;
+ dev_spec->shadow_ram[i].modified = false;
dev_spec->shadow_ram[i].value = 0xFFFF;
}
if (mac->type == e1000_ich8lan)
mac->rar_entry_count--;
/* Set if manageability features are enabled. */
- mac->arc_subsystem_valid = 1;
+ mac->arc_subsystem_valid = true;
/* LED operations */
switch (mac->type) {
/* Enable PCS Lock-loss workaround for ICH8 */
if (mac->type == e1000_ich8lan)
- e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
+ e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
return 0;
}
*/
ret_val = e1000e_config_fc_after_link_up(hw);
if (ret_val)
- hw_dbg(hw, "Error configuring flow control\n");
+ e_dbg("Error configuring flow control\n");
out:
return ret_val;
u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
s32 ret_val = 0;
- might_sleep();
-
mutex_lock(&swflag_mutex);
while (timeout) {
}
if (!timeout) {
- hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
+ e_dbg("SW/FW/HW has locked the resource for too long.\n");
ret_val = -E1000_ERR_CONFIG;
goto out;
}
}
if (!timeout) {
- hw_dbg(hw, "Failed to acquire the semaphore.\n");
+ e_dbg("Failed to acquire the semaphore.\n");
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
ew32(EXTCNF_CTRL, extcnf_ctrl);
ret_val = -E1000_ERR_CONFIG;
**/
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
{
- u32 fwsm = er32(FWSM);
+ u32 fwsm;
+
+ fwsm = er32(FWSM);
return (fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
if (ret_val)
return ret_val;
- hw_dbg(hw, "IFE PMC: %X\n", data);
+ e_dbg("IFE PMC: %X\n", data);
udelay(1);
if (phy->autoneg_wait_to_complete) {
- hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
+ e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
ret_val = e1000e_phy_has_link_generic(hw,
PHY_FORCE_LIMIT,
return ret_val;
if (!link)
- hw_dbg(hw, "Link taking longer than expected.\n");
+ e_dbg("Link taking longer than expected.\n");
/* Try once more */
ret_val = e1000e_phy_has_link_generic(hw,
s32 ret_val;
u16 word_addr, reg_data, reg_addr, phy_page = 0;
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
reg_addr &= PHY_REG_MASK;
reg_addr |= phy_page;
- ret_val = phy->ops.write_phy_reg_locked(hw,
+ ret_val = phy->ops.write_reg_locked(hw,
(u32)reg_addr,
reg_data);
if (ret_val)
}
out:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
return ret_val;
}
goto out;
/* Wrap the whole flow with the sw flag */
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
goto out;
/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
if (link) {
if (hw->phy.type == e1000_phy_82578) {
- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
- BM_CS_STATUS,
+ ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
&status_reg);
if (ret_val)
goto release;
}
if (hw->phy.type == e1000_phy_82577) {
- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
- HV_M_STATUS,
+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
&status_reg);
if (ret_val)
goto release;
}
/* Link stall fix for link up */
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
0x0100);
if (ret_val)
goto release;
} else {
/* Link stall fix for link down */
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
0x4100);
if (ret_val)
goto release;
ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
release:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
out:
return ret_val;
}
*
* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
**/
-static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
+s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
{
s32 ret_val = 0;
u32 ctrl_reg = 0;
if (hw->mac.type != e1000_pchlan)
return ret_val;
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
mac_reg = er32(PHY_CTRL);
- ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
goto out;
/* Restart auto-neg to activate the bits */
if (!e1000_check_reset_block(hw))
oem_reg |= HV_OEM_BITS_RESTART_AN;
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
+ ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
out:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
return ret_val;
}
}
/* Select page 0 */
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
if (ret_val)
goto out;
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
/*
* Configure the K1 Si workaround during phy reset assuming there is
* leave the PHY in a bad state possibly resulting in no link.
*/
if (loop == 0)
- hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
+ e_dbg("LAN_INIT_DONE not set, increase timeout\n");
/* Clear the Init Done bit for the next init event */
data = er32(STATUS);
return ret_val;
if (!link) {
- hw_dbg(hw, "Phy info is only valid if link is up\n");
+ e_dbg("Phy info is only valid if link is up\n");
return -E1000_ERR_CONFIG;
}
/**
* e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure
- * @active: TRUE to enable LPLU, FALSE to disable
+ * @active: true to enable LPLU, false to disable
*
* Sets the LPLU D0 state according to the active flag. When
* activating LPLU this function also disables smart speed
/**
* e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
* @hw: pointer to the HW structure
- * @active: TRUE to enable LPLU, FALSE to disable
+ * @active: true to enable LPLU, false to disable
*
* Sets the LPLU D3 state according to the active flag. When
* activating LPLU this function also disables smart speed
return 0;
}
- hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
+ e_dbg("Unable to determine valid NVM bank via EEC - "
"reading flash signature\n");
/* fall-thru */
default:
return 0;
}
- hw_dbg(hw, "ERROR: No valid NVM bank present\n");
+ e_dbg("ERROR: No valid NVM bank present\n");
return -E1000_ERR_NVM;
}
if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
(words == 0)) {
- hw_dbg(hw, "nvm parameter(s) out of bounds\n");
+ e_dbg("nvm parameter(s) out of bounds\n");
ret_val = -E1000_ERR_NVM;
goto out;
}
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
- hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
+ e_dbg("Could not detect valid bank, assuming bank 0\n");
bank = 0;
}
}
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
out:
if (ret_val)
- hw_dbg(hw, "NVM read error: %d\n", ret_val);
+ e_dbg("NVM read error: %d\n", ret_val);
return ret_val;
}
/* Check if the flash descriptor is valid */
if (hsfsts.hsf_status.fldesvalid == 0) {
- hw_dbg(hw, "Flash descriptor invalid. "
+ e_dbg("Flash descriptor invalid. "
"SW Sequencing must be used.");
return -E1000_ERR_NVM;
}
hsfsts.hsf_status.flcdone = 1;
ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
} else {
- hw_dbg(hw, "Flash controller busy, cannot get access");
+ e_dbg("Flash controller busy, cannot get access");
}
}
/* Repeat for some time before giving up. */
continue;
} else if (hsfsts.hsf_status.flcdone == 0) {
- hw_dbg(hw, "Timeout error - flash cycle "
+ e_dbg("Timeout error - flash cycle "
"did not complete.");
break;
}
if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
(words == 0)) {
- hw_dbg(hw, "nvm parameter(s) out of bounds\n");
+ e_dbg("nvm parameter(s) out of bounds\n");
return -E1000_ERR_NVM;
}
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
for (i = 0; i < words; i++) {
- dev_spec->shadow_ram[offset+i].modified = 1;
+ dev_spec->shadow_ram[offset+i].modified = true;
dev_spec->shadow_ram[offset+i].value = data[i];
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
return 0;
}
if (nvm->type != e1000_nvm_flash_sw)
goto out;
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
/*
* We're writing to the opposite bank so if we're on bank 1,
*/
ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
- hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
+ e_dbg("Could not detect valid bank, assuming bank 0\n");
bank = 0;
}
old_bank_offset = 0;
ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
} else {
new_bank_offset = 0;
ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
}
*/
if (ret_val) {
/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
- hw_dbg(hw, "Flash commit failed.\n");
- nvm->ops.release_nvm(hw);
+ e_dbg("Flash commit failed.\n");
+ nvm->ops.release(hw);
goto out;
}
act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
data &= 0xBFFF;
act_offset * 2 + 1,
(u8)(data >> 8));
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
/* Great! Everything worked, we can now clear the cached entries. */
for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
- dev_spec->shadow_ram[i].modified = 0;
+ dev_spec->shadow_ram[i].modified = false;
dev_spec->shadow_ram[i].value = 0xFFFF;
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
/*
* Reload the EEPROM, or else modifications will not appear
out:
if (ret_val)
- hw_dbg(hw, "NVM update error: %d\n", ret_val);
+ e_dbg("NVM update error: %d\n", ret_val);
return ret_val;
}
union ich8_hws_flash_status hsfsts;
u32 gfpreg;
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
gfpreg = er32flash(ICH_FLASH_GFPREG);
hsfsts.hsf_status.flockdn = true;
ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
}
/**
/* Repeat for some time before giving up. */
continue;
if (hsfsts.hsf_status.flcdone == 0) {
- hw_dbg(hw, "Timeout error - flash cycle "
+ e_dbg("Timeout error - flash cycle "
"did not complete.");
break;
}
return ret_val;
for (program_retries = 0; program_retries < 100; program_retries++) {
- hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
+ e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
udelay(100);
ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
if (!ret_val)
u32 flash_bank_size = nvm->flash_bank_size * 2;
s32 ret_val;
s32 count = 0;
- s32 iteration;
- s32 sector_size;
- s32 j;
+ s32 j, iteration, sector_size;
hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
- hw_dbg(hw, "NVM Read Error\n");
+ e_dbg("NVM Read Error\n");
return ret_val;
}
*/
ret_val = e1000e_disable_pcie_master(hw);
if (ret_val) {
- hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+ e_dbg("PCI-E Master disable polling has failed.\n");
}
- hw_dbg(hw, "Masking off all interrupts\n");
+ e_dbg("Masking off all interrupts\n");
ew32(IMC, 0xffffffff);
/*
}
ret_val = e1000_acquire_swflag_ich8lan(hw);
/* Whether or not the swflag was acquired, we need to reset the part */
- hw_dbg(hw, "Issuing a global reset to ich8lan\n");
+ e_dbg("Issuing a global reset to ich8lan\n");
ew32(CTRL, (ctrl | E1000_CTRL_RST));
msleep(20);
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
- hw_dbg(hw, "Auto Read Done did not complete\n");
+ e_dbg("Auto Read Done did not complete\n");
}
}
/* Dummy read to clear the phy wakeup bit after lcd reset */
/* Initialize identification LED */
ret_val = mac->ops.id_led_init(hw);
- if (ret_val) {
- hw_dbg(hw, "Error initializing identification LED\n");
- return ret_val;
- }
+ if (ret_val)
+ e_dbg("Error initializing identification LED\n");
+ /* This is not fatal and we should not stop init due to this */
/* Setup the receive address. */
e1000e_init_rx_addrs(hw, mac->rar_entry_count);
/* Zero out the Multicast HASH table */
- hw_dbg(hw, "Zeroing the MTA\n");
+ e_dbg("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
* Reset the phy after disabling host wakeup to reset the Rx buffer.
*/
if (hw->phy.type == e1000_phy_82578) {
- hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
+ hw->phy.ops.read_reg(hw, BM_WUC, &i);
ret_val = e1000_phy_hw_reset_ich8lan(hw);
if (ret_val)
return ret_val;
*/
hw->fc.current_mode = hw->fc.requested_mode;
- hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
+ e_dbg("After fix-ups FlowControl is now = %x\n",
hw->fc.current_mode);
/* Continue to configure the copper link. */
ew32(FCTTV, hw->fc.pause_time);
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82577)) {
- ret_val = hw->phy.ops.write_phy_reg(hw,
+ ret_val = hw->phy.ops.write_reg(hw,
PHY_REG(BM_PORT_CTRL_PAGE, 27),
hw->fc.pause_time);
if (ret_val)
return ret_val;
break;
case e1000_phy_ife:
- ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
+ ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
®_data);
if (ret_val)
return ret_val;
reg_data |= IFE_PMC_AUTO_MDIX;
break;
}
- ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
+ ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
reg_data);
if (ret_val)
return ret_val;
* @hw: pointer to the HW structure
* @state: boolean value used to set the current Kumeran workaround state
*
- * If ICH8, set the current Kumeran workaround state (enabled - TRUE
- * /disabled - FALSE).
+ * If ICH8, set the current Kumeran workaround state (enabled - true
+ * /disabled - false).
**/
void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
bool state)
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
if (hw->mac.type != e1000_ich8lan) {
- hw_dbg(hw, "Workaround applies to ICH8 only.\n");
+ e_dbg("Workaround applies to ICH8 only.\n");
return;
}
**/
static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
{
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
(u16)hw->mac.ledctl_mode1);
}
**/
static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
{
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
(u16)hw->mac.ledctl_default);
}
}
}
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
}
/**
}
}
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
}
/**
if (status & E1000_STATUS_PHYRA)
ew32(STATUS, status & ~E1000_STATUS_PHYRA);
else
- hw_dbg(hw,
- "PHY Reset Asserted not set - needs delay\n");
+ e_dbg("PHY Reset Asserted not set - needs delay\n");
}
e1000e_get_cfg_done(hw);
} else {
if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
/* Maybe we should do a basic PHY config */
- hw_dbg(hw, "EEPROM not present\n");
+ e_dbg("EEPROM not present\n");
return -E1000_ERR_CONFIG;
}
}
**/
static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
{
- u32 temp;
u16 phy_data;
e1000e_clear_hw_cntrs_base(hw);
- temp = er32(ALGNERRC);
- temp = er32(RXERRC);
- temp = er32(TNCRS);
- temp = er32(CEXTERR);
- temp = er32(TSCTC);
- temp = er32(TSCTFC);
+ er32(ALGNERRC);
+ er32(RXERRC);
+ er32(TNCRS);
+ er32(CEXTERR);
+ er32(TSCTC);
+ er32(TSCTFC);
- temp = er32(MGTPRC);
- temp = er32(MGTPDC);
- temp = er32(MGTPTC);
+ er32(MGTPRC);
+ er32(MGTPDC);
+ er32(MGTPTC);
- temp = er32(IAC);
- temp = er32(ICRXOC);
+ er32(IAC);
+ er32(ICRXOC);
/* Clear PHY statistics registers */
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82577)) {
- hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
}
}
};
static struct e1000_phy_operations ich8_phy_ops = {
- .acquire_phy = e1000_acquire_swflag_ich8lan,
+ .acquire = e1000_acquire_swflag_ich8lan,
.check_reset_block = e1000_check_reset_block_ich8lan,
- .commit_phy = NULL,
+ .commit = NULL,
.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
.get_cfg_done = e1000_get_cfg_done_ich8lan,
.get_cable_length = e1000e_get_cable_length_igp_2,
- .get_phy_info = e1000_get_phy_info_ich8lan,
- .read_phy_reg = e1000e_read_phy_reg_igp,
- .release_phy = e1000_release_swflag_ich8lan,
- .reset_phy = e1000_phy_hw_reset_ich8lan,
+ .get_info = e1000_get_phy_info_ich8lan,
+ .read_reg = e1000e_read_phy_reg_igp,
+ .release = e1000_release_swflag_ich8lan,
+ .reset = e1000_phy_hw_reset_ich8lan,
.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
- .write_phy_reg = e1000e_write_phy_reg_igp,
+ .write_reg = e1000e_write_phy_reg_igp,
};
static struct e1000_nvm_operations ich8_nvm_ops = {
- .acquire_nvm = e1000_acquire_nvm_ich8lan,
- .read_nvm = e1000_read_nvm_ich8lan,
- .release_nvm = e1000_release_nvm_ich8lan,
- .update_nvm = e1000_update_nvm_checksum_ich8lan,
+ .acquire = e1000_acquire_nvm_ich8lan,
+ .read = e1000_read_nvm_ich8lan,
+ .release = e1000_release_nvm_ich8lan,
+ .update = e1000_update_nvm_checksum_ich8lan,
.valid_led_default = e1000_valid_led_default_ich8lan,
- .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
- .write_nvm = e1000_write_nvm_ich8lan,
+ .validate = e1000_validate_nvm_checksum_ich8lan,
+ .write = e1000_write_nvm_ich8lan,
};
struct e1000_info e1000_ich8_info = {
git.openpandora.org / pandora-kernel.git / blobdiff