-/*
+/*
* Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
*
* Copyright © 2006 Red Hat, Inc.
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
#include <asm/io.h>
#define CAFE_NAND_CTRL1 0x00
#define CAFE_NAND_READ_DATA 0x1000
#define CAFE_NAND_WRITE_DATA 0x2000
+#define CAFE_GLOBAL_CTRL 0x3004
+#define CAFE_GLOBAL_IRQ 0x3008
+#define CAFE_GLOBAL_IRQ_MASK 0x300c
+#define CAFE_NAND_RESET 0x3034
+
int cafe_correct_ecc(unsigned char *buf,
unsigned short *chk_syndrome_list);
int page_addr;
dma_addr_t dmaaddr;
unsigned char *dmabuf;
-
};
static int usedma = 1;
static int debug = 0;
module_param(debug, int, 0644);
+static int regdebug = 0;
+module_param(regdebug, int, 0644);
+
static int checkecc = 1;
module_param(checkecc, int, 0644);
-static int slowtiming = 0;
-module_param(slowtiming, int, 0644);
+static int numtimings;
+static int timing[3];
+module_param_array(timing, int, &numtimings, 0644);
/* Hrm. Why isn't this already conditional on something in the struct device? */
#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
+/* Make it easier to switch to PIO if we need to */
+#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
+#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
static int cafe_device_ready(struct mtd_info *mtd)
{
struct cafe_priv *cafe = mtd->priv;
- int result = !!(readl(cafe->mmio + CAFE_NAND_STATUS) | 0x40000000);
- uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
+ int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
+ uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
- writel(irqs, cafe->mmio+CAFE_NAND_IRQ);
+ cafe_writel(cafe, irqs, NAND_IRQ);
cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
- result?"":" not", irqs, readl(cafe->mmio + CAFE_NAND_IRQ),
- readl(cafe->mmio + 0x3008), readl(cafe->mmio + 0x300c));
+ result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
+ cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
return result;
}
if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
/* Second half of a command we already calculated */
- writel(cafe->ctl2 | 0x100 | command, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
ctl1 = cafe->ctl1;
+ cafe->ctl2 &= ~(1<<30);
cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
cafe->ctl1, cafe->nr_data);
goto do_command;
}
/* Reset ECC engine */
- writel(0, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, 0, NAND_CTRL2);
/* Emulate NAND_CMD_READOOB on large-page chips */
if (mtd->writesize > 512 &&
for small-page chips, to position the buffer correctly? */
if (column != -1) {
- writel(column, cafe->mmio + CAFE_NAND_ADDR1);
+ cafe_writel(cafe, column, NAND_ADDR1);
adrbytes = 2;
if (page_addr != -1)
goto write_adr2;
} else if (page_addr != -1) {
- writel(page_addr & 0xffff, cafe->mmio + CAFE_NAND_ADDR1);
+ cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
page_addr >>= 16;
write_adr2:
- writel(page_addr, cafe->mmio+0x20);
+ cafe_writel(cafe, page_addr, NAND_ADDR2);
adrbytes += 2;
if (mtd->size > mtd->writesize << 16)
adrbytes++;
ctl1 |= ((adrbytes-1)|8) << 27;
if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
- /* Ignore the first command of a pair; the hardware
+ /* Ignore the first command of a pair; the hardware
deals with them both at once, later */
cafe->ctl1 = ctl1;
- cafe->ctl2 = 0;
cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
cafe->ctl1, cafe->datalen);
return;
}
/* RNDOUT and READ0 commands need a following byte */
if (command == NAND_CMD_RNDOUT)
- writel(cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
- writel(cafe->ctl2 | 0x100 | NAND_CMD_READSTART, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
do_command:
-#if 0
- /* http://dev.laptop.org/ticket/200
- ECC on read only works if we read precisely 0x80e bytes */
- if (cafe->datalen == 2112)
- cafe->datalen = 2062;
-#endif
- cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
- cafe->datalen, ctl1, readl(cafe->mmio+CAFE_NAND_CTRL2));
+ cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
+ cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
/* NB: The datasheet lies -- we really should be subtracting 1 here */
- writel(cafe->datalen, cafe->mmio + CAFE_NAND_DATA_LEN);
- writel(0x90000000, cafe->mmio + CAFE_NAND_IRQ);
+ cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
+ cafe_writel(cafe, 0x90000000, NAND_IRQ);
if (usedma && (ctl1 & (3<<25))) {
uint32_t dmactl = 0xc0000000 + cafe->datalen;
/* If WR or RD bits set, set up DMA */
the command. */
doneint = 0x10000000;
}
- writel(dmactl, cafe->mmio + CAFE_NAND_DMA_CTRL);
+ cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
}
cafe->datalen = 0;
-#if 0
- { int i;
- printk("About to write command %08x\n", ctl1);
- for (i=0; i< 0x5c; i+=4)
- printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
+ if (unlikely(regdebug)) {
+ int i;
+ printk("About to write command %08x to register 0\n", ctl1);
+ for (i=4; i< 0x5c; i+=4)
+ printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
}
-#endif
- writel(ctl1, cafe->mmio + CAFE_NAND_CTRL1);
+
+ cafe_writel(cafe, ctl1, NAND_CTRL1);
/* Apply this short delay always to ensure that we do wait tWB in
* any case on any machine. */
ndelay(100);
if (1) {
- int c = 500000;
+ int c;
uint32_t irqs;
- while (c--) {
- irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
+ for (c = 500000; c != 0; c--) {
+ irqs = cafe_readl(cafe, NAND_IRQ);
if (irqs & doneint)
break;
udelay(1);
cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
cpu_relax();
}
- writel(doneint, cafe->mmio + CAFE_NAND_IRQ);
- cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", command, 50000-c, irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
+ cafe_writel(cafe, doneint, NAND_IRQ);
+ cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
+ command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
}
-
- cafe->ctl2 &= ~(1<<8);
- cafe->ctl2 &= ~(1<<30);
+ WARN_ON(cafe->ctl2 & (1<<30));
switch (command) {
case NAND_CMD_STATUS_ERROR1:
case NAND_CMD_STATUS_ERROR2:
case NAND_CMD_STATUS_ERROR3:
- writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
return;
}
nand_wait_ready(mtd);
- writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
+ cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
}
static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
// cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
}
-static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
+static int cafe_nand_interrupt(int irq, void *id)
{
struct mtd_info *mtd = id;
struct cafe_priv *cafe = mtd->priv;
- uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
- writel(irqs & ~0x90000000, cafe->mmio + CAFE_NAND_IRQ);
+ uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
+ cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
if (!irqs)
return IRQ_NONE;
- cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
+ cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
return IRQ_HANDLED;
}
struct cafe_priv *cafe = mtd->priv;
cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
- readl(cafe->mmio + CAFE_NAND_ECC_RESULT),
- readl(cafe->mmio + CAFE_NAND_ECC_SYN01));
+ cafe_readl(cafe, NAND_ECC_RESULT),
+ cafe_readl(cafe, NAND_ECC_SYN01));
chip->read_buf(mtd, buf, mtd->writesize);
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
- if (checkecc && readl(cafe->mmio + CAFE_NAND_ECC_RESULT) & (1<<18)) {
+ if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
unsigned short syn[8];
int i;
for (i=0; i<8; i+=2) {
- uint32_t tmp = readl(cafe->mmio + CAFE_NAND_ECC_SYN01 + (i*2));
+ uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
syn[i] = tmp & 0xfff;
syn[i+1] = (tmp >> 16) & 0xfff;
- }
+ }
if ((i = cafe_correct_ecc(buf, syn)) < 0) {
- dev_dbg(&cafe->pdev->dev, "Failed to correct ECC\n");
+ dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
+ cafe_readl(cafe, NAND_ADDR2) * 2048);
+ for (i=0; i< 0x5c; i+=4)
+ printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
mtd->ecc_stats.failed++;
} else {
dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
.oobfree = {{14, 50}}
};
-/* Ick. The BBT code really ought to be able to work this bit out
+/* Ick. The BBT code really ought to be able to work this bit out
for itself from the above, at least for the 2KiB case */
static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
/* Set up ECC autogeneration */
- cafe->ctl2 |= (1<<27) | (1<<30);
- if (mtd->writesize == 2048)
- cafe->ctl2 |= (1<<29);
+ cafe->ctl2 |= (1<<30);
}
static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
cafe->nand.options |= NAND_SKIP_BBTSCAN;
cafe->nand.block_bad = cafe_nand_block_bad;
}
-
- /* Start off by resetting the NAND controller completely */
- writel(1, cafe->mmio + 0x3034);
- writel(0, cafe->mmio + 0x3034);
- /* Timings from Marvell's test code (not verified or calculated by us) */
- writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
+ if (numtimings && numtimings != 3) {
+ dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
+ }
- if (!slowtiming) {
- writel(0x01010a0a, cafe->mmio + CAFE_NAND_TIMING1);
- writel(0x24121212, cafe->mmio + CAFE_NAND_TIMING2);
- writel(0x11000000, cafe->mmio + CAFE_NAND_TIMING3);
+ if (numtimings == 3) {
+ cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
+ timing[0], timing[1], timing[2]);
} else {
- writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING1);
- writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING2);
- writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING3);
+ timing[0] = cafe_readl(cafe, NAND_TIMING1);
+ timing[1] = cafe_readl(cafe, NAND_TIMING2);
+ timing[2] = cafe_readl(cafe, NAND_TIMING3);
+
+ if (timing[0] | timing[1] | timing[2]) {
+ cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
+ timing[0], timing[1], timing[2]);
+ } else {
+ dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
+ timing[0] = timing[1] = timing[2] = 0xffffffff;
+ }
}
- writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
- err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
+
+ /* Start off by resetting the NAND controller completely */
+ cafe_writel(cafe, 1, NAND_RESET);
+ cafe_writel(cafe, 0, NAND_RESET);
+
+ cafe_writel(cafe, timing[0], NAND_TIMING1);
+ cafe_writel(cafe, timing[1], NAND_TIMING2);
+ cafe_writel(cafe, timing[2], NAND_TIMING3);
+
+ cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
+ err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
+ "CAFE NAND", mtd);
if (err) {
dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
-
goto out_free_dma;
}
-#if 1
+
/* Disable master reset, enable NAND clock */
- ctrl = readl(cafe->mmio + 0x3004);
+ ctrl = cafe_readl(cafe, GLOBAL_CTRL);
ctrl &= 0xffffeff0;
ctrl |= 0x00007000;
- writel(ctrl | 0x05, cafe->mmio + 0x3004);
- writel(ctrl | 0x0a, cafe->mmio + 0x3004);
- writel(0, cafe->mmio + CAFE_NAND_DMA_CTRL);
+ cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
+ cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
+ cafe_writel(cafe, 0, NAND_DMA_CTRL);
- writel(0x7006, cafe->mmio + 0x3004);
- writel(0x700a, cafe->mmio + 0x3004);
+ cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
+ cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
/* Set up DMA address */
- writel(cafe->dmaaddr & 0xffffffff, cafe->mmio + CAFE_NAND_DMA_ADDR0);
+ cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
if (sizeof(cafe->dmaaddr) > 4)
/* Shift in two parts to shut the compiler up */
- writel((cafe->dmaaddr >> 16) >> 16, cafe->mmio + CAFE_NAND_DMA_ADDR1);
+ cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
else
- writel(0, cafe->mmio + CAFE_NAND_DMA_ADDR1);
+ cafe_writel(cafe, 0, NAND_DMA_ADDR1);
cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
- readl(cafe->mmio + CAFE_NAND_DMA_ADDR0), cafe->dmabuf);
+ cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
/* Enable NAND IRQ in global IRQ mask register */
- writel(0x80000007, cafe->mmio + 0x300c);
+ cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
- readl(cafe->mmio + 0x3004), readl(cafe->mmio + 0x300c));
-#endif
-#if 1
- mtd->writesize=2048;
- mtd->oobsize = 0x40;
- memset(cafe->dmabuf, 0x5a, 2112);
- cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
-#endif
-#if 0
- cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
- // nand_wait_ready(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
- cafe->nand.read_byte(mtd);
-#endif
-#if 0
- writel(0x84600070, cafe->mmio);
- udelay(10);
- cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", readl(cafe->mmio + 0x30));
-#endif
- /* Scan to find existance of the device */
+ cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
+
+ /* Scan to find existence of the device */
if (nand_scan_ident(mtd, 1)) {
err = -ENXIO;
goto out_irq;
out_irq:
/* Disable NAND IRQ in global IRQ mask register */
- writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
+ cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
free_irq(pdev->irq, mtd);
out_free_dma:
dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
del_mtd_device(mtd);
/* Disable NAND IRQ in global IRQ mask register */
- writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
+ cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
free_irq(pdev->irq, mtd);
nand_release(mtd);
pci_iounmap(pdev, cafe->mmio);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
-MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
-
-/* Correct ECC for 2048 bytes of 0xff:
- 41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
-
-/* dwmw2's B-test board, in case of completely screwing it:
-Bad eraseblock 2394 at 0x12b40000
-Bad eraseblock 2627 at 0x14860000
-Bad eraseblock 3349 at 0x1a2a0000
-*/
+MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
git.openpandora.org / pandora-kernel.git / blobdiff