Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb

[pandora-kernel.git] / drivers / media / dvb / ttpci / budget-patch.c

diff --git a/drivers/media/dvb/ttpci/budget-patch.c b/drivers/media/dvb/ttpci/budget-patch.c
index fc1267b..39bd0a2 100644 (file)
--- a/drivers/media/dvb/ttpci/budget-patch.c
+++ b/drivers/media/dvb/ttpci/budget-patch.c
@@ -431,22 +431,22 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
        // in budget patch GPIO3 is connected to VSYNC_B
        count = 0;
 #if 0
-       WRITE_RPS1(cpu_to_le32(CMD_UPLOAD |
-         MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 ));
+       WRITE_RPS1(CMD_UPLOAD |
+         MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 );
 #endif
-       WRITE_RPS1(cpu_to_le32(CMD_PAUSE | EVT_VBI_B));
-       WRITE_RPS1(cpu_to_le32(CMD_WR_REG_MASK | (GPIO_CTRL>>2)));
-       WRITE_RPS1(cpu_to_le32(GPIO3_MSK));
-       WRITE_RPS1(cpu_to_le32(SAA7146_GPIO_OUTLO<<24));
+       WRITE_RPS1(CMD_PAUSE | EVT_VBI_B);
+       WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
+       WRITE_RPS1(GPIO3_MSK);
+       WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
 #if RPS_IRQ
        // issue RPS1 interrupt to increment counter
-       WRITE_RPS1(cpu_to_le32(CMD_INTERRUPT));
+       WRITE_RPS1(CMD_INTERRUPT);
        // at least a NOP is neede between two interrupts
-       WRITE_RPS1(cpu_to_le32(CMD_NOP));
+       WRITE_RPS1(CMD_NOP);
        // interrupt again
-       WRITE_RPS1(cpu_to_le32(CMD_INTERRUPT));
+       WRITE_RPS1(CMD_INTERRUPT);
 #endif
-       WRITE_RPS1(cpu_to_le32(CMD_STOP));
+       WRITE_RPS1(CMD_STOP);
 
 #if RPS_IRQ
        // set event counter 1 source as RPS1 interrupt (0x03)          (rE4 p53)
@@ -500,14 +500,14 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
 
 /*      New design (By Emard)
 **      this rps1 code will copy internal HS event to GPIO3 pin.
-**      GPIO3 is in budget-patch hardware connectd to port B VSYNC
+**      GPIO3 is in budget-patch hardware connected to port B VSYNC
 
 **      HS is an internal event of 7146, accessible with RPS
 **      and temporarily raised high every n lines
 **      (n in defined in the RPS_THRESH1 counter threshold)
 **      I think HS is raised high on the beginning of the n-th line
 **      and remains high until this n-th line that triggered
-**      it is completely received. When the receiption of n-th line
+**      it is completely received. When the reception of n-th line
 **      ends, HS is lowered.
 
 **      To transmit data over DMA, 7146 needs changing state at
@@ -541,7 +541,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
 **      hardware debug note: a working budget card (including budget patch)
 **      with vpeirq() interrupt setup in mode "0x90" (every 64K) will
 **      generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
-**      and that means 3*25=75 Hz of interrupt freqency, as seen by
+**      and that means 3*25=75 Hz of interrupt frequency, as seen by
 **      watch cat /proc/interrupts
 **
 **      If this frequency is 3x lower (and data received in the DMA
@@ -550,7 +550,7 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
 **      this means VSYNC line is not connected in the hardware.
 **      (check soldering pcb and pins)
 **      The same behaviour of missing VSYNC can be duplicated on budget
-**      cards, by seting DD1_INIT trigger mode 7 in 3rd nibble.
+**      cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
 */
 
        // Setup RPS1 "program" (p35)
@@ -558,28 +558,28 @@ static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_exte
 
 
        // Wait Source Line Counter Threshold                           (p36)
-       WRITE_RPS1(cpu_to_le32(CMD_PAUSE | EVT_HS));
+       WRITE_RPS1(CMD_PAUSE | EVT_HS);
        // Set GPIO3=1                                                  (p42)
-       WRITE_RPS1(cpu_to_le32(CMD_WR_REG_MASK | (GPIO_CTRL>>2)));
-       WRITE_RPS1(cpu_to_le32(GPIO3_MSK));
-       WRITE_RPS1(cpu_to_le32(SAA7146_GPIO_OUTHI<<24));
+       WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
+       WRITE_RPS1(GPIO3_MSK);
+       WRITE_RPS1(SAA7146_GPIO_OUTHI<<24);
 #if RPS_IRQ
        // issue RPS1 interrupt
-       WRITE_RPS1(cpu_to_le32(CMD_INTERRUPT));
+       WRITE_RPS1(CMD_INTERRUPT);
 #endif
        // Wait reset Source Line Counter Threshold                     (p36)
-       WRITE_RPS1(cpu_to_le32(CMD_PAUSE | RPS_INV | EVT_HS));
+       WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS);
        // Set GPIO3=0                                                  (p42)
-       WRITE_RPS1(cpu_to_le32(CMD_WR_REG_MASK | (GPIO_CTRL>>2)));
-       WRITE_RPS1(cpu_to_le32(GPIO3_MSK));
-       WRITE_RPS1(cpu_to_le32(SAA7146_GPIO_OUTLO<<24));
+       WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
+       WRITE_RPS1(GPIO3_MSK);
+       WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
 #if RPS_IRQ
        // issue RPS1 interrupt
-       WRITE_RPS1(cpu_to_le32(CMD_INTERRUPT));
+       WRITE_RPS1(CMD_INTERRUPT);
 #endif
        // Jump to begin of RPS program                                 (p37)
-       WRITE_RPS1(cpu_to_le32(CMD_JUMP));
-       WRITE_RPS1(cpu_to_le32(dev->d_rps1.dma_handle));
+       WRITE_RPS1(CMD_JUMP);
+       WRITE_RPS1(dev->d_rps1.dma_handle);
 
        // Fix VSYNC level
        saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);