Merge master.kernel.org:/pub/scm/linux/kernel/git/sfrench/cifs-2.6

[pandora-kernel.git] / drivers / media / dvb / frontends / dib3000mc.c

diff --git a/drivers/media/dvb/frontends/dib3000mc.c b/drivers/media/dvb/frontends/dib3000mc.c
index 60e10db..054d7e6 100644 (file)
--- a/drivers/media/dvb/frontends/dib3000mc.c
+++ b/drivers/media/dvb/frontends/dib3000mc.c
@@ -37,6 +37,8 @@ struct dib3000mc_state {
 
        struct dibx000_i2c_master i2c_master;
 
+       u32 timf;
+
        fe_bandwidth_t current_bandwidth;
 
        u16 dev_id;
@@ -92,50 +94,31 @@ static int dib3000mc_identify(struct dib3000mc_state *state)
 
 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw, u8 update_offset)
 {
-/*
-       u32 timf_msb, timf_lsb, i;
-       int tim_sgn ;
-       LUInt comp1, comp2, comp ;
-//     u32 tim_offset ;
-       comp = 27700 * BW_INDEX_TO_KHZ(bw) / 1000;
-       timf_msb = (comp >> 16) & 0x00FF;
-       timf_lsb =  comp        & 0xFFFF;
-
-       // Update the timing offset ;
-       if (update_offset) {
-               if (state->timing_offset_comp_done == 0) {
-                       usleep(200000);
-                       state->timing_offset_comp_done = 1;
-               }
-               tim_offset = dib3000mc_read_word(state, 416);
-               if ((tim_offset & 0x2000) == 0x2000)
-                       tim_offset |= 0xC000; // PB: This only works if tim_offset is s16 - weird
+       u32 timf;
 
-               if (nfft == 0)
-                       tim_offset = tim_offset << 2; // PB: Do not store the offset for different things in one variable
-               state->timing_offset += tim_offset;
-       }
-       tim_offset = state->timing_offset;
-
-       if (tim_offset < 0) {
-               tim_sgn = 1;
-               tim_offset = -tim_offset;
+       if (state->timf == 0) {
+               timf = 1384402; // default value for 8MHz
+               if (update_offset)
+                       msleep(200); // first time we do an update
        } else
-               tim_sgn = 0;
+               timf = state->timf;
 
-       comp1 = tim_offset * timf_lsb;
-       comp2 = tim_offset * timf_msb;
-       comp  = ((comp1 >> 16) + comp2) >> 7;
+       timf *= (BW_INDEX_TO_KHZ(bw) / 1000);
 
-       if (tim_sgn == 0)
-               comp = timf_msb * (1<<16) + timf_lsb + comp;
-       else
-               comp = timf_msb * (1<<16) + timf_lsb - comp;
+       if (update_offset) {
+               s16 tim_offs = dib3000mc_read_word(state, 416);
+
+               if (tim_offs &  0x2000)
+                       tim_offs -= 0x4000;
+
+               if (nfft == 0)
+                       tim_offs *= 4;
 
-       timf_msb = (comp>>16)&0xFF ;
-       timf_lsb = comp&0xFFFF;
-*/
-       u32 timf = 1384402 * (BW_INDEX_TO_KHZ(bw) / 1000);
+               timf += tim_offs;
+               state->timf = timf / (BW_INDEX_TO_KHZ(bw) / 1000);
+       }
+
+       dprintk("timf: %d\n", timf);
 
        dib3000mc_write_word(state, 23, timf >> 16);
        dib3000mc_write_word(state, 24, timf & 0xffff);
@@ -143,15 +126,18 @@ static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw,
        return 0;
 }
 
-static int dib3000mc_setup_pwm3_state(struct dib3000mc_state *state)
+static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state)
 {
+       u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb;
     if (state->cfg->pwm3_inversion) {
-               dib3000mc_write_word(state, 51, (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0));
-               dib3000mc_write_word(state, 52, (0 << 8) | (5 << 5) | (1 << 4) | (1 << 3) | (1 << 2) | (2 << 0));
+               reg_51 =  (2 << 14) | (0 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
+               reg_52 |= (1 << 2);
        } else {
-               dib3000mc_write_word(state, 51, (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0));
-               dib3000mc_write_word(state, 52, (1 << 8) | (5 << 5) | (1 << 4) | (1 << 3) | (0 << 2) | (2 << 0));
+               reg_51 = (2 << 14) | (4 << 10) | (7 << 6) | (2 << 2) | (2 << 0);
+               reg_52 |= (1 << 8);
        }
+       dib3000mc_write_word(state, 51, reg_51);
+       dib3000mc_write_word(state, 52, reg_52);
 
     if (state->cfg->use_pwm3)
                dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
@@ -326,10 +312,10 @@ static int dib3000mc_init(struct dvb_frontend *demod)
                dib3000mc_write_word(state, 175,  0x0000);
                dib3000mc_write_word(state, 1032, 0x012C);
        }
-       dib3000mc_write_word(state, 1033, 0);
+       dib3000mc_write_word(state, 1033, 0x0000);
 
        // P_clk_cfg
-       dib3000mc_write_word(state, 1037, 12592);
+       dib3000mc_write_word(state, 1037, 0x3130);
 
        // other configurations
 
@@ -350,7 +336,7 @@ static int dib3000mc_init(struct dvb_frontend *demod)
        dib3000mc_write_word(state, 50, 0x8000);
 
        // agc setup misc
-       dib3000mc_setup_pwm3_state(state);
+       dib3000mc_setup_pwm_state(state);
 
        // P_agc_counter_lock
        dib3000mc_write_word(state, 53, 0x87);
@@ -359,7 +345,7 @@ static int dib3000mc_init(struct dvb_frontend *demod)
 
        /* agc */
        dib3000mc_write_word(state, 36, state->cfg->max_time);
-       dib3000mc_write_word(state, 37, agc->setup);
+       dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
        dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
        dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
 
@@ -426,10 +412,9 @@ static int dib3000mc_sleep(struct dvb_frontend *demod)
 {
        struct dib3000mc_state *state = demod->demodulator_priv;
 
-       dib3000mc_write_word(state, 1037, dib3000mc_read_word(state, 1037) | 0x0003);
        dib3000mc_write_word(state, 1031, 0xFFFF);
        dib3000mc_write_word(state, 1032, 0xFFFF);
-       dib3000mc_write_word(state, 1033, 0xFFF4);   // ****  Bin2
+       dib3000mc_write_word(state, 1033, 0xFFF0);
 
     return 0;
 }
@@ -490,7 +475,7 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx
        tmp = ((chan->nfft & 0x1) << 7) | (chan->guard << 5) | (chan->nqam << 3) | chan->vit_alpha;
        dib3000mc_write_word(state, 0, tmp);
 
-       dib3000mc_write_word(state, 5, seq);
+       dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
 
        tmp = (chan->vit_hrch << 4) | (chan->vit_select_hp);
        if (!chan->vit_hrch || (chan->vit_hrch && chan->vit_select_hp))
@@ -526,19 +511,15 @@ static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dibx000
 
 
        /* a channel for autosearch */
-       reg = 0;
-       if (chan->nfft == -1 && chan->guard == -1) reg = 7;
-       if (chan->nfft == -1 && chan->guard != -1) reg = 2;
-       if (chan->nfft != -1 && chan->guard == -1) reg = 3;
-
        fchan.nfft = 1; fchan.guard = 0; fchan.nqam = 2;
        fchan.vit_alpha = 1; fchan.vit_code_rate_hp = 2; fchan.vit_code_rate_lp = 2;
        fchan.vit_hrch = 0; fchan.vit_select_hp = 1;
 
-       dib3000mc_set_channel_cfg(state, &fchan, reg);
+       dib3000mc_set_channel_cfg(state, &fchan, 11);
 
        reg = dib3000mc_read_word(state, 0);
        dib3000mc_write_word(state, 0, reg | (1 << 8));
+       dib3000mc_read_word(state, 511);
        dib3000mc_write_word(state, 0, reg);
 
        return 0;
@@ -578,8 +559,8 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channe
                dib3000mc_write_word(state, 33, 6);
        }
 
-       // if (lock)
-       //      dib3000mc_set_timing(state, ch->nfft, ch->Bw, 1);
+       if (dib3000mc_read_word(state, 509) & 0x80)
+               dib3000mc_set_timing(state, ch->nfft, ch->Bw, 1);
 
        return 0;
 }
@@ -841,6 +822,8 @@ struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr
 
        dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr);
 
+       dib3000mc_write_word(st, 1037, 0x3130);
+
        return demod;
 
 error: