Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[pandora-kernel.git] / drivers / iommu / intel-iommu.c

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index f28d933..be1953c 100644 (file)
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -939,7 +939,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
 
        addr = iommu->root_entry;
 
-       spin_lock_irqsave(&iommu->register_lock, flag);
+       raw_spin_lock_irqsave(&iommu->register_lock, flag);
        dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 
        writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
@@ -948,7 +948,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                      readl, (sts & DMA_GSTS_RTPS), sts);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flag);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
@@ -959,14 +959,14 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
        if (!rwbf_quirk && !cap_rwbf(iommu->cap))
                return;
 
-       spin_lock_irqsave(&iommu->register_lock, flag);
+       raw_spin_lock_irqsave(&iommu->register_lock, flag);
        writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                      readl, (!(val & DMA_GSTS_WBFS)), val);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flag);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -993,14 +993,14 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
        }
        val |= DMA_CCMD_ICC;
 
-       spin_lock_irqsave(&iommu->register_lock, flag);
+       raw_spin_lock_irqsave(&iommu->register_lock, flag);
        dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
                dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flag);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -1039,7 +1039,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
        if (cap_write_drain(iommu->cap))
                val |= DMA_TLB_WRITE_DRAIN;
 
-       spin_lock_irqsave(&iommu->register_lock, flag);
+       raw_spin_lock_irqsave(&iommu->register_lock, flag);
        /* Note: Only uses first TLB reg currently */
        if (val_iva)
                dmar_writeq(iommu->reg + tlb_offset, val_iva);
@@ -1049,7 +1049,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
        IOMMU_WAIT_OP(iommu, tlb_offset + 8,
                dmar_readq, (!(val & DMA_TLB_IVT)), val);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flag);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 
        /* check IOTLB invalidation granularity */
        if (DMA_TLB_IAIG(val) == 0)
@@ -1165,7 +1165,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
        u32 pmen;
        unsigned long flags;
 
-       spin_lock_irqsave(&iommu->register_lock, flags);
+       raw_spin_lock_irqsave(&iommu->register_lock, flags);
        pmen = readl(iommu->reg + DMAR_PMEN_REG);
        pmen &= ~DMA_PMEN_EPM;
        writel(pmen, iommu->reg + DMAR_PMEN_REG);
@@ -1174,7 +1174,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
        IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
                readl, !(pmen & DMA_PMEN_PRS), pmen);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flags);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 static int iommu_enable_translation(struct intel_iommu *iommu)
@@ -1182,7 +1182,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
        u32 sts;
        unsigned long flags;
 
-       spin_lock_irqsave(&iommu->register_lock, flags);
+       raw_spin_lock_irqsave(&iommu->register_lock, flags);
        iommu->gcmd |= DMA_GCMD_TE;
        writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1190,7 +1190,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                      readl, (sts & DMA_GSTS_TES), sts);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flags);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
        return 0;
 }
 
@@ -1199,7 +1199,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
        u32 sts;
        unsigned long flag;
 
-       spin_lock_irqsave(&iommu->register_lock, flag);
+       raw_spin_lock_irqsave(&iommu->register_lock, flag);
        iommu->gcmd &= ~DMA_GCMD_TE;
        writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1207,7 +1207,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                      readl, (!(sts & DMA_GSTS_TES)), sts);
 
-       spin_unlock_irqrestore(&iommu->register_lock, flag);
+       raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
        return 0;
 }
 
@@ -3329,7 +3329,7 @@ static int iommu_suspend(void)
        for_each_active_iommu(iommu, drhd) {
                iommu_disable_translation(iommu);
 
-               spin_lock_irqsave(&iommu->register_lock, flag);
+               raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                iommu->iommu_state[SR_DMAR_FECTL_REG] =
                        readl(iommu->reg + DMAR_FECTL_REG);
@@ -3340,7 +3340,7 @@ static int iommu_suspend(void)
                iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
                        readl(iommu->reg + DMAR_FEUADDR_REG);
 
-               spin_unlock_irqrestore(&iommu->register_lock, flag);
+               raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
        }
        return 0;
 
@@ -3367,7 +3367,7 @@ static void iommu_resume(void)
 
        for_each_active_iommu(iommu, drhd) {
 
-               spin_lock_irqsave(&iommu->register_lock, flag);
+               raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
                        iommu->reg + DMAR_FECTL_REG);
@@ -3378,7 +3378,7 @@ static void iommu_resume(void)
                writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
                        iommu->reg + DMAR_FEUADDR_REG);
 
-               spin_unlock_irqrestore(&iommu->register_lock, flag);
+               raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
        }
 
        for_each_active_iommu(iommu, drhd)