Merge branch 'stable-3.2' into pandora-3.2
[pandora-kernel.git] / drivers / idle / intel_idle.c
index 5b39216..4fa2b11 100644 (file)
@@ -163,6 +163,38 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
                .enter = &intel_idle },
 };
 
+static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
+       { /* MWAIT C0 */ },
+       { /* MWAIT C1 */
+               .name = "C1-IVB",
+               .desc = "MWAIT 0x00",
+               .flags = CPUIDLE_FLAG_TIME_VALID,
+               .exit_latency = 1,
+               .target_residency = 1,
+               .enter = &intel_idle },
+       { /* MWAIT C2 */
+               .name = "C3-IVB",
+               .desc = "MWAIT 0x10",
+               .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 59,
+               .target_residency = 156,
+               .enter = &intel_idle },
+       { /* MWAIT C3 */
+               .name = "C6-IVB",
+               .desc = "MWAIT 0x20",
+               .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 80,
+               .target_residency = 300,
+               .enter = &intel_idle },
+       { /* MWAIT C4 */
+               .name = "C7-IVB",
+               .desc = "MWAIT 0x30",
+               .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 87,
+               .target_residency = 300,
+               .enter = &intel_idle },
+};
+
 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
        { /* MWAIT C0 */ },
        { /* MWAIT C1 */
@@ -386,6 +418,11 @@ static int intel_idle_probe(void)
                cpuidle_state_table = snb_cstates;
                break;
 
+       case 0x3A:      /* IVB */
+       case 0x3E:      /* IVB Xeon */
+               cpuidle_state_table = ivb_cstates;
+               break;
+
        default:
                pr_debug(PREFIX "does not run on family %d model %d\n",
                        boot_cpu_data.x86, boot_cpu_data.x86_model);
@@ -394,10 +431,8 @@ static int intel_idle_probe(void)
 
        if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
                lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
-       else {
+       else
                on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
-               register_cpu_notifier(&setup_broadcast_notifier);
-       }
 
        pr_debug(PREFIX "v" INTEL_IDLE_VERSION
                " model 0x%X\n", boot_cpu_data.x86_model);
@@ -560,6 +595,9 @@ static int __init intel_idle_init(void)
                return retval;
        }
 
+       if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
+               register_cpu_notifier(&setup_broadcast_notifier);
+
        return 0;
 }