Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-2.6-fixes
[pandora-kernel.git] / drivers / gpu / drm / radeon / rv515.c
index 9035121..7d9a7b0 100644 (file)
@@ -147,16 +147,11 @@ void rv515_gpu_init(struct radeon_device *rdev)
 {
        unsigned pipe_select_current, gb_pipe_select, tmp;
 
-       r100_hdp_reset(rdev);
-       r100_rb2d_reset(rdev);
-
        if (r100_gui_wait_for_idle(rdev)) {
                printk(KERN_WARNING "Failed to wait GUI idle while "
                       "reseting GPU. Bad things might happen.\n");
        }
-
        rv515_vga_render_disable(rdev);
-
        r420_pipes_init(rdev);
        gb_pipe_select = RREG32(0x402C);
        tmp = RREG32(0x170C);
@@ -174,91 +169,6 @@ void rv515_gpu_init(struct radeon_device *rdev)
        }
 }
 
-int rv515_ga_reset(struct radeon_device *rdev)
-{
-       uint32_t tmp;
-       bool reinit_cp;
-       int i;
-
-       reinit_cp = rdev->cp.ready;
-       rdev->cp.ready = false;
-       for (i = 0; i < rdev->usec_timeout; i++) {
-               WREG32(CP_CSQ_MODE, 0);
-               WREG32(CP_CSQ_CNTL, 0);
-               WREG32(RBBM_SOFT_RESET, 0x32005);
-               (void)RREG32(RBBM_SOFT_RESET);
-               udelay(200);
-               WREG32(RBBM_SOFT_RESET, 0);
-               /* Wait to prevent race in RBBM_STATUS */
-               mdelay(1);
-               tmp = RREG32(RBBM_STATUS);
-               if (tmp & ((1 << 20) | (1 << 26))) {
-                       DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
-                       /* GA still busy soft reset it */
-                       WREG32(0x429C, 0x200);
-                       WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
-                       WREG32(0x43E0, 0);
-                       WREG32(0x43E4, 0);
-                       WREG32(0x24AC, 0);
-               }
-               /* Wait to prevent race in RBBM_STATUS */
-               mdelay(1);
-               tmp = RREG32(RBBM_STATUS);
-               if (!(tmp & ((1 << 20) | (1 << 26)))) {
-                       break;
-               }
-       }
-       for (i = 0; i < rdev->usec_timeout; i++) {
-               tmp = RREG32(RBBM_STATUS);
-               if (!(tmp & ((1 << 20) | (1 << 26)))) {
-                       DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
-                                tmp);
-                       DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
-                       DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
-                       DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
-                       if (reinit_cp) {
-                               return r100_cp_init(rdev, rdev->cp.ring_size);
-                       }
-                       return 0;
-               }
-               DRM_UDELAY(1);
-       }
-       tmp = RREG32(RBBM_STATUS);
-       DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
-       return -1;
-}
-
-int rv515_gpu_reset(struct radeon_device *rdev)
-{
-       uint32_t status;
-
-       /* reset order likely matter */
-       status = RREG32(RBBM_STATUS);
-       /* reset HDP */
-       r100_hdp_reset(rdev);
-       /* reset rb2d */
-       if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
-               r100_rb2d_reset(rdev);
-       }
-       /* reset GA */
-       if (status & ((1 << 20) | (1 << 26))) {
-               rv515_ga_reset(rdev);
-       }
-       /* reset CP */
-       status = RREG32(RBBM_STATUS);
-       if (status & (1 << 16)) {
-               r100_cp_reset(rdev);
-       }
-       /* Check if GPU is idle */
-       status = RREG32(RBBM_STATUS);
-       if (status & (1 << 31)) {
-               DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
-               return -1;
-       }
-       DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
-       return 0;
-}
-
 static void rv515_vram_get_type(struct radeon_device *rdev)
 {
        uint32_t tmp;
@@ -335,7 +245,7 @@ static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 
        tmp = RREG32(0x2140);
        seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
-       radeon_gpu_reset(rdev);
+       radeon_asic_reset(rdev);
        tmp = RREG32(0x425C);
        seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
        return 0;
@@ -503,7 +413,7 @@ int rv515_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        rv515_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -535,7 +445,6 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 
 void rv515_fini(struct radeon_device *rdev)
 {
-       radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
@@ -573,7 +482,7 @@ int rv515_init(struct radeon_device *rdev)
                return -EINVAL;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
@@ -584,8 +493,6 @@ int rv515_init(struct radeon_device *rdev)
                return -EINVAL;
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
-       /* Initialize power management */
-       radeon_pm_init(rdev);
        /* initialize AGP */
        if (rdev->flags & RADEON_IS_AGP) {
                r = radeon_agp_init(rdev);
@@ -885,20 +792,20 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
                return;
        }
 
-       if (crtc->vsc.full > rfixed_const(2))
-               wm->num_line_pair.full = rfixed_const(2);
+       if (crtc->vsc.full > dfixed_const(2))
+               wm->num_line_pair.full = dfixed_const(2);
        else
-               wm->num_line_pair.full = rfixed_const(1);
-
-       b.full = rfixed_const(mode->crtc_hdisplay);
-       c.full = rfixed_const(256);
-       a.full = rfixed_div(b, c);
-       request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
-       request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
-       if (a.full < rfixed_const(4)) {
+               wm->num_line_pair.full = dfixed_const(1);
+
+       b.full = dfixed_const(mode->crtc_hdisplay);
+       c.full = dfixed_const(256);
+       a.full = dfixed_div(b, c);
+       request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
+       request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
+       if (a.full < dfixed_const(4)) {
                wm->lb_request_fifo_depth = 4;
        } else {
-               wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
+               wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
        }
 
        /* Determine consumption rate
@@ -907,23 +814,23 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
         *  vsc = vertical scaling ratio, defined as source/destination
         *  hsc = horizontal scaling ration, defined as source/destination
         */
-       a.full = rfixed_const(mode->clock);
-       b.full = rfixed_const(1000);
-       a.full = rfixed_div(a, b);
-       pclk.full = rfixed_div(b, a);
+       a.full = dfixed_const(mode->clock);
+       b.full = dfixed_const(1000);
+       a.full = dfixed_div(a, b);
+       pclk.full = dfixed_div(b, a);
        if (crtc->rmx_type != RMX_OFF) {
-               b.full = rfixed_const(2);
+               b.full = dfixed_const(2);
                if (crtc->vsc.full > b.full)
                        b.full = crtc->vsc.full;
-               b.full = rfixed_mul(b, crtc->hsc);
-               c.full = rfixed_const(2);
-               b.full = rfixed_div(b, c);
-               consumption_time.full = rfixed_div(pclk, b);
+               b.full = dfixed_mul(b, crtc->hsc);
+               c.full = dfixed_const(2);
+               b.full = dfixed_div(b, c);
+               consumption_time.full = dfixed_div(pclk, b);
        } else {
                consumption_time.full = pclk.full;
        }
-       a.full = rfixed_const(1);
-       wm->consumption_rate.full = rfixed_div(a, consumption_time);
+       a.full = dfixed_const(1);
+       wm->consumption_rate.full = dfixed_div(a, consumption_time);
 
 
        /* Determine line time
@@ -931,27 +838,27 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
         *  LineTime = total number of horizontal pixels
         *  pclk = pixel clock period(ns)
         */
-       a.full = rfixed_const(crtc->base.mode.crtc_htotal);
-       line_time.full = rfixed_mul(a, pclk);
+       a.full = dfixed_const(crtc->base.mode.crtc_htotal);
+       line_time.full = dfixed_mul(a, pclk);
 
        /* Determine active time
         *  ActiveTime = time of active region of display within one line,
         *  hactive = total number of horizontal active pixels
         *  htotal = total number of horizontal pixels
         */
-       a.full = rfixed_const(crtc->base.mode.crtc_htotal);
-       b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
-       wm->active_time.full = rfixed_mul(line_time, b);
-       wm->active_time.full = rfixed_div(wm->active_time, a);
+       a.full = dfixed_const(crtc->base.mode.crtc_htotal);
+       b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
+       wm->active_time.full = dfixed_mul(line_time, b);
+       wm->active_time.full = dfixed_div(wm->active_time, a);
 
        /* Determine chunk time
         * ChunkTime = the time it takes the DCP to send one chunk of data
         * to the LB which consists of pipeline delay and inter chunk gap
         * sclk = system clock(Mhz)
         */
-       a.full = rfixed_const(600 * 1000);
-       chunk_time.full = rfixed_div(a, rdev->pm.sclk);
-       read_delay_latency.full = rfixed_const(1000);
+       a.full = dfixed_const(600 * 1000);
+       chunk_time.full = dfixed_div(a, rdev->pm.sclk);
+       read_delay_latency.full = dfixed_const(1000);
 
        /* Determine the worst case latency
         * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
@@ -961,9 +868,9 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
         * ChunkTime = time it takes the DCP to send one chunk of data to the LB
         *             which consists of pipeline delay and inter chunk gap
         */
-       if (rfixed_trunc(wm->num_line_pair) > 1) {
-               a.full = rfixed_const(3);
-               wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
+       if (dfixed_trunc(wm->num_line_pair) > 1) {
+               a.full = dfixed_const(3);
+               wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
                wm->worst_case_latency.full += read_delay_latency.full;
        } else {
                wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
@@ -979,34 +886,34 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
         *              of data to the LB which consists of
         *  pipeline delay and inter chunk gap
         */
-       if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
+       if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
                tolerable_latency.full = line_time.full;
        } else {
-               tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
+               tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
                tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
-               tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
+               tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
                tolerable_latency.full = line_time.full - tolerable_latency.full;
        }
        /* We assume worst case 32bits (4 bytes) */
-       wm->dbpp.full = rfixed_const(2 * 16);
+       wm->dbpp.full = dfixed_const(2 * 16);
 
        /* Determine the maximum priority mark
         *  width = viewport width in pixels
         */
-       a.full = rfixed_const(16);
-       wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
-       wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
-       wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
+       a.full = dfixed_const(16);
+       wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
+       wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
+       wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
 
        /* Determine estimated width */
        estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
-       estimated_width.full = rfixed_div(estimated_width, consumption_time);
-       if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
+       estimated_width.full = dfixed_div(estimated_width, consumption_time);
+       if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
                wm->priority_mark.full = wm->priority_mark_max.full;
        } else {
-               a.full = rfixed_const(16);
-               wm->priority_mark.full = rfixed_div(estimated_width, a);
-               wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
+               a.full = dfixed_const(16);
+               wm->priority_mark.full = dfixed_div(estimated_width, a);
+               wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
                wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
        }
 }
@@ -1035,58 +942,58 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
        WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
 
        if (mode0 && mode1) {
-               if (rfixed_trunc(wm0.dbpp) > 64)
-                       a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
+               if (dfixed_trunc(wm0.dbpp) > 64)
+                       a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
                else
                        a.full = wm0.num_line_pair.full;
-               if (rfixed_trunc(wm1.dbpp) > 64)
-                       b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
+               if (dfixed_trunc(wm1.dbpp) > 64)
+                       b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
                else
                        b.full = wm1.num_line_pair.full;
                a.full += b.full;
-               fill_rate.full = rfixed_div(wm0.sclk, a);
+               fill_rate.full = dfixed_div(wm0.sclk, a);
                if (wm0.consumption_rate.full > fill_rate.full) {
                        b.full = wm0.consumption_rate.full - fill_rate.full;
-                       b.full = rfixed_mul(b, wm0.active_time);
-                       a.full = rfixed_const(16);
-                       b.full = rfixed_div(b, a);
-                       a.full = rfixed_mul(wm0.worst_case_latency,
+                       b.full = dfixed_mul(b, wm0.active_time);
+                       a.full = dfixed_const(16);
+                       b.full = dfixed_div(b, a);
+                       a.full = dfixed_mul(wm0.worst_case_latency,
                                                wm0.consumption_rate);
                        priority_mark02.full = a.full + b.full;
                } else {
-                       a.full = rfixed_mul(wm0.worst_case_latency,
+                       a.full = dfixed_mul(wm0.worst_case_latency,
                                                wm0.consumption_rate);
-                       b.full = rfixed_const(16 * 1000);
-                       priority_mark02.full = rfixed_div(a, b);
+                       b.full = dfixed_const(16 * 1000);
+                       priority_mark02.full = dfixed_div(a, b);
                }
                if (wm1.consumption_rate.full > fill_rate.full) {
                        b.full = wm1.consumption_rate.full - fill_rate.full;
-                       b.full = rfixed_mul(b, wm1.active_time);
-                       a.full = rfixed_const(16);
-                       b.full = rfixed_div(b, a);
-                       a.full = rfixed_mul(wm1.worst_case_latency,
+                       b.full = dfixed_mul(b, wm1.active_time);
+                       a.full = dfixed_const(16);
+                       b.full = dfixed_div(b, a);
+                       a.full = dfixed_mul(wm1.worst_case_latency,
                                                wm1.consumption_rate);
                        priority_mark12.full = a.full + b.full;
                } else {
-                       a.full = rfixed_mul(wm1.worst_case_latency,
+                       a.full = dfixed_mul(wm1.worst_case_latency,
                                                wm1.consumption_rate);
-                       b.full = rfixed_const(16 * 1000);
-                       priority_mark12.full = rfixed_div(a, b);
+                       b.full = dfixed_const(16 * 1000);
+                       priority_mark12.full = dfixed_div(a, b);
                }
                if (wm0.priority_mark.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark.full;
-               if (rfixed_trunc(priority_mark02) < 0)
+               if (dfixed_trunc(priority_mark02) < 0)
                        priority_mark02.full = 0;
                if (wm0.priority_mark_max.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark_max.full;
                if (wm1.priority_mark.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark.full;
-               if (rfixed_trunc(priority_mark12) < 0)
+               if (dfixed_trunc(priority_mark12) < 0)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
-               d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
-               d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+               d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
+               d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
                if (rdev->disp_priority == 2) {
                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
@@ -1096,32 +1003,32 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
                WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
        } else if (mode0) {
-               if (rfixed_trunc(wm0.dbpp) > 64)
-                       a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
+               if (dfixed_trunc(wm0.dbpp) > 64)
+                       a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
                else
                        a.full = wm0.num_line_pair.full;
-               fill_rate.full = rfixed_div(wm0.sclk, a);
+               fill_rate.full = dfixed_div(wm0.sclk, a);
                if (wm0.consumption_rate.full > fill_rate.full) {
                        b.full = wm0.consumption_rate.full - fill_rate.full;
-                       b.full = rfixed_mul(b, wm0.active_time);
-                       a.full = rfixed_const(16);
-                       b.full = rfixed_div(b, a);
-                       a.full = rfixed_mul(wm0.worst_case_latency,
+                       b.full = dfixed_mul(b, wm0.active_time);
+                       a.full = dfixed_const(16);
+                       b.full = dfixed_div(b, a);
+                       a.full = dfixed_mul(wm0.worst_case_latency,
                                                wm0.consumption_rate);
                        priority_mark02.full = a.full + b.full;
                } else {
-                       a.full = rfixed_mul(wm0.worst_case_latency,
+                       a.full = dfixed_mul(wm0.worst_case_latency,
                                                wm0.consumption_rate);
-                       b.full = rfixed_const(16);
-                       priority_mark02.full = rfixed_div(a, b);
+                       b.full = dfixed_const(16);
+                       priority_mark02.full = dfixed_div(a, b);
                }
                if (wm0.priority_mark.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark.full;
-               if (rfixed_trunc(priority_mark02) < 0)
+               if (dfixed_trunc(priority_mark02) < 0)
                        priority_mark02.full = 0;
                if (wm0.priority_mark_max.full > priority_mark02.full)
                        priority_mark02.full = wm0.priority_mark_max.full;
-               d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
+               d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
                if (rdev->disp_priority == 2)
                        d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
                WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
@@ -1129,32 +1036,32 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
                WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
                WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
        } else {
-               if (rfixed_trunc(wm1.dbpp) > 64)
-                       a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
+               if (dfixed_trunc(wm1.dbpp) > 64)
+                       a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
                else
                        a.full = wm1.num_line_pair.full;
-               fill_rate.full = rfixed_div(wm1.sclk, a);
+               fill_rate.full = dfixed_div(wm1.sclk, a);
                if (wm1.consumption_rate.full > fill_rate.full) {
                        b.full = wm1.consumption_rate.full - fill_rate.full;
-                       b.full = rfixed_mul(b, wm1.active_time);
-                       a.full = rfixed_const(16);
-                       b.full = rfixed_div(b, a);
-                       a.full = rfixed_mul(wm1.worst_case_latency,
+                       b.full = dfixed_mul(b, wm1.active_time);
+                       a.full = dfixed_const(16);
+                       b.full = dfixed_div(b, a);
+                       a.full = dfixed_mul(wm1.worst_case_latency,
                                                wm1.consumption_rate);
                        priority_mark12.full = a.full + b.full;
                } else {
-                       a.full = rfixed_mul(wm1.worst_case_latency,
+                       a.full = dfixed_mul(wm1.worst_case_latency,
                                                wm1.consumption_rate);
-                       b.full = rfixed_const(16 * 1000);
-                       priority_mark12.full = rfixed_div(a, b);
+                       b.full = dfixed_const(16 * 1000);
+                       priority_mark12.full = dfixed_div(a, b);
                }
                if (wm1.priority_mark.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark.full;
-               if (rfixed_trunc(priority_mark12) < 0)
+               if (dfixed_trunc(priority_mark12) < 0)
                        priority_mark12.full = 0;
                if (wm1.priority_mark_max.full > priority_mark12.full)
                        priority_mark12.full = wm1.priority_mark_max.full;
-               d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
+               d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
                if (rdev->disp_priority == 2)
                        d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
                WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);