Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...

[pandora-kernel.git] / drivers / gpu / drm / radeon / evergreen.c

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 941080a..43fd016 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -43,17 +43,6 @@ static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
 
 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 {
-       struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
-       u32 tmp;
-
-       /* make sure flip is at vb rather than hb */
-       tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
-       tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
-       WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
-
-       /* set pageflip to happen anywhere in vblank interval */
-       WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
-
        /* enable the pflip int */
        radeon_irq_kms_pflip_irq_get(rdev, crtc);
 }
@@ -131,11 +120,16 @@ void evergreen_pm_misc(struct radeon_device *rdev)
        struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
        struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 
-       if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
-               if (voltage->voltage != rdev->pm.current_vddc) {
-                       radeon_atom_set_voltage(rdev, voltage->voltage);
+       if (voltage->type == VOLTAGE_SW) {
+               if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
+                       radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
                        rdev->pm.current_vddc = voltage->voltage;
-                       DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
+                       DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
+               }
+               if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
+                       radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
+                       rdev->pm.current_vddci = voltage->vddci;
+                       DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
                }
        }
 }
@@ -359,7 +353,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
                                        struct drm_display_mode *mode,
                                        struct drm_display_mode *other_mode)
 {
-       u32 tmp = 0;
+       u32 tmp;
        /*
         * Line Buffer Setup
         * There are 3 line buffers, each one shared by 2 display controllers.
@@ -369,64 +363,63 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
         * first display controller
         *  0 - first half of lb (3840 * 2)
         *  1 - first 3/4 of lb (5760 * 2)
-        *  2 - whole lb (7680 * 2)
+        *  2 - whole lb (7680 * 2), other crtc must be disabled
         *  3 - first 1/4 of lb (1920 * 2)
         * second display controller
         *  4 - second half of lb (3840 * 2)
         *  5 - second 3/4 of lb (5760 * 2)
-        *  6 - whole lb (7680 * 2)
+        *  6 - whole lb (7680 * 2), other crtc must be disabled
         *  7 - last 1/4 of lb (1920 * 2)
         */
-       if (mode && other_mode) {
-               if (mode->hdisplay > other_mode->hdisplay) {
-                       if (mode->hdisplay > 2560)
-                               tmp = 1; /* 3/4 */
-                       else
-                               tmp = 0; /* 1/2 */
-               } else if (other_mode->hdisplay > mode->hdisplay) {
-                       if (other_mode->hdisplay > 2560)
-                               tmp = 3; /* 1/4 */
-                       else
-                               tmp = 0; /* 1/2 */
-               } else
+       /* this can get tricky if we have two large displays on a paired group
+        * of crtcs.  Ideally for multiple large displays we'd assign them to
+        * non-linked crtcs for maximum line buffer allocation.
+        */
+       if (radeon_crtc->base.enabled && mode) {
+               if (other_mode)
                        tmp = 0; /* 1/2 */
-       } else if (mode)
-               tmp = 2; /* whole */
-       else if (other_mode)
-               tmp = 3; /* 1/4 */
+               else
+                       tmp = 2; /* whole */
+       } else
+               tmp = 0;
 
        /* second controller of the pair uses second half of the lb */
        if (radeon_crtc->crtc_id % 2)
                tmp += 4;
        WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 
-       switch (tmp) {
-       case 0:
-       case 4:
-       default:
-               if (ASIC_IS_DCE5(rdev))
-                       return 4096 * 2;
-               else
-                       return 3840 * 2;
-       case 1:
-       case 5:
-               if (ASIC_IS_DCE5(rdev))
-                       return 6144 * 2;
-               else
-                       return 5760 * 2;
-       case 2:
-       case 6:
-               if (ASIC_IS_DCE5(rdev))
-                       return 8192 * 2;
-               else
-                       return 7680 * 2;
-       case 3:
-       case 7:
-               if (ASIC_IS_DCE5(rdev))
-                       return 2048 * 2;
-               else
-                       return 1920 * 2;
+       if (radeon_crtc->base.enabled && mode) {
+               switch (tmp) {
+               case 0:
+               case 4:
+               default:
+                       if (ASIC_IS_DCE5(rdev))
+                               return 4096 * 2;
+                       else
+                               return 3840 * 2;
+               case 1:
+               case 5:
+                       if (ASIC_IS_DCE5(rdev))
+                               return 6144 * 2;
+                       else
+                               return 5760 * 2;
+               case 2:
+               case 6:
+                       if (ASIC_IS_DCE5(rdev))
+                               return 8192 * 2;
+                       else
+                               return 7680 * 2;
+               case 3:
+               case 7:
+                       if (ASIC_IS_DCE5(rdev))
+                               return 2048 * 2;
+                       else
+                               return 1920 * 2;
+               }
        }
+
+       /* controller not enabled, so no lb used */
+       return 0;
 }
 
 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
@@ -3047,9 +3040,6 @@ int evergreen_init(struct radeon_device *rdev)
 {
        int r;
 
-       r = radeon_dummy_page_init(rdev);
-       if (r)
-               return r;
        /* This don't do much */
        r = radeon_gem_init(rdev);
        if (r)
@@ -3161,7 +3151,6 @@ void evergreen_fini(struct radeon_device *rdev)
        radeon_atombios_fini(rdev);
        kfree(rdev->bios);
        rdev->bios = NULL;
-       radeon_dummy_page_fini(rdev);
 }
 
 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)