drm/radeon/kms/DCE4.1: ss is not supported on the internal pplls

[pandora-kernel.git] / drivers / gpu / drm / radeon / atombios_crtc.c

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9541995..a515b2a 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -466,7 +466,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
                        return;
                }
                args.v2.ucEnable = enable;
-               if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
+               if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
                        args.v2.ucEnable = ATOM_DISABLE;
        } else if (ASIC_IS_DCE3(rdev)) {
                args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
@@ -764,7 +764,7 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
 }
 
 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
-                                     int crtc_id,
+                                     u32 crtc_id,
                                      int pll_id,
                                      u32 encoder_mode,
                                      u32 encoder_id,
@@ -851,8 +851,7 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
                        args.v5.ucPpll = pll_id;
                        break;
                case 6:
-                       args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
-                       args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
+                       args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
                        args.v6.ucRefDiv = ref_div;
                        args.v6.usFbDiv = cpu_to_le16(fb_div);
                        args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);