Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued

[pandora-kernel.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef5f69a..e9a95df 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3532,6 +3532,7 @@ enum skl_disp_power_wells {
 #define   BLM_POLARITY_PNV                     (1 << 0) /* pnv only */
 
 #define BLC_HIST_CTL   (dev_priv->info.display_mmio_offset + 0x61260)
+#define  BLM_HISTOGRAM_ENABLE                  (1 << 31)
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -7031,6 +7032,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)                ((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)       ((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT                     0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL            (1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS                      0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER                    0x45404 /* CTL2 */