drm/i915: Correct the bit number for the MI_FLUSH_ENABLE.

[pandora-kernel.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a10f5f..56d931a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -399,7 +399,7 @@
 
 #define MI_MODE                0x0209c
 # define VS_TIMER_DISPATCH                             (1 << 6)
-# define MI_FLUSH_ENABLE                               (1 << 11)
+# define MI_FLUSH_ENABLE                               (1 << 12)
 
 #define GEN6_GT_MODE   0x20d0
 #define   GEN6_GT_MODE_HI      (1 << 9)