Merge branch 'drm-fbdev-cleanup' into drm-core-next

[pandora-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0405a74..1258b11 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -205,6 +205,7 @@ struct intel_device_info {
        u8 is_g4x : 1;
        u8 is_pineview : 1;
        u8 is_ironlake : 1;
        u8 is_g4x : 1;
        u8 is_pineview : 1;
        u8 is_ironlake : 1;

+       u8 is_gen6 : 1;

        u8 has_fbc : 1;
        u8 has_rc6 : 1;
        u8 has_pipe_cxsr : 1;
        u8 has_fbc : 1;
        u8 has_rc6 : 1;
        u8 has_pipe_cxsr : 1;


@@ -220,6 +221,11 @@ enum no_fbc_reason {
        FBC_NOT_TILED, /* buffer not tiled */
 };
 
        FBC_NOT_TILED, /* buffer not tiled */
 };
 

+enum intel_pch {
+       PCH_IBX,        /* Ibexpeak PCH */
+       PCH_CPT,        /* Cougarpoint PCH */
+};
+

 struct intel_fbdev;
 
 typedef struct drm_i915_private {
 struct intel_fbdev;
 
 typedef struct drm_i915_private {


@@ -332,6 +338,9 @@ typedef struct drm_i915_private {
        /* Display functions */
        struct drm_i915_display_funcs display;
 
        /* Display functions */
        struct drm_i915_display_funcs display;
 

+       /* PCH chipset type */
+       enum intel_pch pch_type;
+

        /* Register state */
        bool modeset_on_lid;
        u8 saveLBB;
        /* Register state */
        bool modeset_on_lid;
        u8 saveLBB;


@@ -612,6 +621,8 @@ typedef struct drm_i915_private {
        /* Reclocking support */
        bool render_reclock_avail;
        bool lvds_downclock_avail;
        /* Reclocking support */
        bool render_reclock_avail;
        bool lvds_downclock_avail;

+       /* indicate whether the LVDS EDID is OK */
+       bool lvds_edid_good;

        /* indicates the reduced downclock for LVDS*/
        int lvds_downclock;
        struct work_struct idle_work;
        /* indicates the reduced downclock for LVDS*/
        int lvds_downclock;
        struct work_struct idle_work;


@@ -735,6 +746,8 @@ struct drm_i915_gem_object {
        atomic_t pending_flip;
 };
 
        atomic_t pending_flip;
 };
 

+#define to_intel_bo(x) ((struct drm_i915_gem_object *) (x)->driver_private)
+

 /**
  * Request queue structure.
  *
 /**
  * Request queue structure.
  *


@@ -992,6 +1005,9 @@ extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 extern void i8xx_disable_fbc(struct drm_device *dev);
 extern void g4x_disable_fbc(struct drm_device *dev);
 
 extern void i8xx_disable_fbc(struct drm_device *dev);
 extern void g4x_disable_fbc(struct drm_device *dev);
 

+extern void intel_detect_pch (struct drm_device *dev);
+extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
+

 /**
  * Lock test for when it's just for synchronization of ring access.
  *
 /**
  * Lock test for when it's just for synchronization of ring access.
  *


@@ -1089,6 +1105,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define IS_IRONLAKE_M(dev)     ((dev)->pci_device == 0x0046)
 #define IS_IRONLAKE(dev)       (INTEL_INFO(dev)->is_ironlake)
 #define IS_I9XX(dev)           (INTEL_INFO(dev)->is_i9xx)
 #define IS_IRONLAKE_M(dev)     ((dev)->pci_device == 0x0046)
 #define IS_IRONLAKE(dev)       (INTEL_INFO(dev)->is_ironlake)
 #define IS_I9XX(dev)           (INTEL_INFO(dev)->is_i9xx)

+#define IS_GEN6(dev)           (INTEL_INFO(dev)->is_gen6)

 #define IS_MOBILE(dev)         (INTEL_INFO(dev)->is_mobile)
 
 #define IS_GEN3(dev)   (IS_I915G(dev) ||                       \
 #define IS_MOBILE(dev)         (INTEL_INFO(dev)->is_mobile)
 
 #define IS_GEN3(dev)   (IS_I915G(dev) ||                       \


@@ -1112,8 +1129,6 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 

-#define IS_GEN6(dev)   ((dev)->pci_device == 0x0102)
-

 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */


@@ -1124,7 +1139,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define SUPPORTS_INTEGRATED_DP(dev)    (IS_G4X(dev) || IS_IRONLAKE(dev))
 #define SUPPORTS_EDP(dev)              (IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)               (IS_I9XX(dev) && IS_MOBILE(dev) && \
 #define SUPPORTS_INTEGRATED_DP(dev)    (IS_G4X(dev) || IS_IRONLAKE(dev))
 #define SUPPORTS_EDP(dev)              (IS_IRONLAKE_M(dev))
 #define SUPPORTS_TV(dev)               (IS_I9XX(dev) && IS_MOBILE(dev) && \

-                                       !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
+                                       !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
+                                       !IS_GEN6(dev))

 #define I915_HAS_HOTPLUG(dev)           (INTEL_INFO(dev)->has_hotplug)
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 #define I915_HAS_HOTPLUG(dev)           (INTEL_INFO(dev)->has_hotplug)
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))


@@ -1137,6 +1153,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) ||        \
                            IS_GEN6(dev))
 
 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) ||        \
                            IS_GEN6(dev))
 

+#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
+#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
+

 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
 #endif
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
 #endif