Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[pandora-kernel.git] / drivers / firewire / fw-ohci.h
index 35e2a75..a2fbb62 100644 (file)
@@ -30,6 +30,7 @@
 #define  OHCI1394_HCControl_softReset          0x00010000
 #define OHCI1394_SelfIDBuffer                 0x064
 #define OHCI1394_SelfIDCount                  0x068
+#define  OHCI1394_SelfIDCount_selfIDError      0x80000000
 #define OHCI1394_IRMultiChanMaskHiSet         0x070
 #define OHCI1394_IRMultiChanMaskHiClear       0x074
 #define OHCI1394_IRMultiChanMaskLoSet         0x078
 #define   OHCI1394_LinkControl_cycleSource     (1 << 22)
 #define OHCI1394_NodeID                       0x0E8
 #define   OHCI1394_NodeID_idValid             0x80000000
+#define   OHCI1394_NodeID_nodeNumber          0x0000003f
+#define   OHCI1394_NodeID_busNumber           0x0000ffc0
 #define OHCI1394_PhyControl                   0x0EC
 #define   OHCI1394_PhyControl_Read(addr)       (((addr) << 8) | 0x00008000)
 #define   OHCI1394_PhyControl_ReadDone         0x80000000
 #define   OHCI1394_PhyControl_ReadData(r)      (((r) & 0x00ff0000) >> 16)
-#define   OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
+#define   OHCI1394_PhyControl_Write(addr, data)        (((addr) << 8) | (data) | 0x00004000)
 #define   OHCI1394_PhyControl_WriteDone                0x00004000
 #define OHCI1394_IsochronousCycleTimer        0x0F0
 #define OHCI1394_AsReqFilterHiSet             0x100
 #define OHCI1394_IsoXmitCommandPtr(n)            (0x20C + 16 * (n))
 
 /* Isochronous receive registers */
+#define OHCI1394_IsoRcvContextBase(n)         (0x400 + 32 * (n))
 #define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n))
 #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
 #define OHCI1394_IsoRcvCommandPtr(n)          (0x40C + 32 * (n))
 #define OHCI1394_IsoRcvContextMatch(n)        (0x410 + 32 * (n))
 
 /* Interrupts Mask/Events */
-#define OHCI1394_reqTxComplete           0x00000001
-#define OHCI1394_respTxComplete          0x00000002
-#define OHCI1394_ARRQ                    0x00000004
-#define OHCI1394_ARRS                    0x00000008
-#define OHCI1394_RQPkt                   0x00000010
-#define OHCI1394_RSPkt                   0x00000020
-#define OHCI1394_isochTx                 0x00000040
-#define OHCI1394_isochRx                 0x00000080
-#define OHCI1394_postedWriteErr          0x00000100
-#define OHCI1394_lockRespErr             0x00000200
-#define OHCI1394_selfIDComplete          0x00010000
-#define OHCI1394_busReset                0x00020000
-#define OHCI1394_phy                     0x00080000
-#define OHCI1394_cycleSynch              0x00100000
-#define OHCI1394_cycle64Seconds          0x00200000
-#define OHCI1394_cycleLost               0x00400000
-#define OHCI1394_cycleInconsistent       0x00800000
-#define OHCI1394_unrecoverableError      0x01000000
-#define OHCI1394_cycleTooLong            0x02000000
-#define OHCI1394_phyRegRcvd              0x04000000
-#define OHCI1394_masterIntEnable         0x80000000
+#define OHCI1394_reqTxComplete         0x00000001
+#define OHCI1394_respTxComplete                0x00000002
+#define OHCI1394_ARRQ                  0x00000004
+#define OHCI1394_ARRS                  0x00000008
+#define OHCI1394_RQPkt                 0x00000010
+#define OHCI1394_RSPkt                 0x00000020
+#define OHCI1394_isochTx               0x00000040
+#define OHCI1394_isochRx               0x00000080
+#define OHCI1394_postedWriteErr                0x00000100
+#define OHCI1394_lockRespErr           0x00000200
+#define OHCI1394_selfIDComplete                0x00010000
+#define OHCI1394_busReset              0x00020000
+#define OHCI1394_regAccessFail         0x00040000
+#define OHCI1394_phy                   0x00080000
+#define OHCI1394_cycleSynch            0x00100000
+#define OHCI1394_cycle64Seconds                0x00200000
+#define OHCI1394_cycleLost             0x00400000
+#define OHCI1394_cycleInconsistent     0x00800000
+#define OHCI1394_unrecoverableError    0x01000000
+#define OHCI1394_cycleTooLong          0x02000000
+#define OHCI1394_phyRegRcvd            0x04000000
+#define OHCI1394_masterIntEnable       0x80000000
 
 #define OHCI1394_evt_no_status         0x0
 #define OHCI1394_evt_long_packet       0x2