* Alter this version for the I5000 module when modifications are made
*/
#define I5000_REVISION " Ver: 2.0.12 " __DATE__
+#define EDAC_MOD_STR "i5000_edac"
#define i5000_printk(level, fmt, arg...) \
edac_printk(level, "i5000", fmt, ##arg)
#define FERR_FAT_M3ERR 0x00000004
#define FERR_FAT_M2ERR 0x00000002
#define FERR_FAT_M1ERR 0x00000001
-#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
+#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
FERR_FAT_M2ERR | \
FERR_FAT_M3ERR)
#define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
FERR_NF_M11ERR | \
FERR_NF_M10ERR | \
- FERR_NF_M8ERR | \
+ FERR_NF_M8ERR | \
FERR_NF_M7ERR | \
FERR_NF_M6ERR | \
FERR_NF_M5ERR | \
#define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
FERR_NF_M28ERR)
#define FERR_NF_THERMAL (FERR_NF_M26ERR | \
- FERR_NF_M25ERR | \
+ FERR_NF_M25ERR | \
FERR_NF_M24ERR | \
FERR_NF_M23ERR)
#define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
#define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
#define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
-#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIM_RANKS(mtr) ? 2 : 1)
+#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
/* Table of devices attributes supported by this driver */
static const struct i5000_dev_info i5000_devs[] = {
[I5000P] = {
- .ctl_name = "I5000",
- .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
- },
+ .ctl_name = "I5000",
+ .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
+ },
};
struct i5000_dimm_info {
struct pci_dev *branch_0; /* 21.0 */
struct pci_dev *branch_1; /* 22.0 */
- int node_id; /* ID of this node */
-
u16 tolm; /* top of low memory */
u64 ambase; /* AMB BAR */
u16 b1_ambpresent0; /* Branch 1, Channel 8 */
u16 b1_ambpresent1; /* Branch 1, Channel 1 */
- /* DIMM infomation matrix, allocating architecture maximums */
+ /* DIMM information matrix, allocating architecture maximums */
struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
/* Actual values for this controller */
};
-/******************************************************************************
+static struct edac_pci_ctl_info *i5000_pci;
+
+/*
* i5000_get_error_info Retrieve the hardware error information from
* the hardware and cache it in the 'info'
* structure
*/
static void i5000_get_error_info(struct mem_ctl_info *mci,
- struct i5000_error_info * info)
+ struct i5000_error_info *info)
{
struct i5000_pvt *pvt;
u32 value;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
/* read in the 1st FATAL error register */
pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
/* harvest the various error data we need */
pci_read_config_dword(pvt->branchmap_werrors,
- NERR_FAT_FBD, &info->nerr_fat_fbd);
+ NERR_FAT_FBD, &info->nerr_fat_fbd);
pci_read_config_word(pvt->branchmap_werrors,
- NRECMEMA, &info->nrecmema);
+ NRECMEMA, &info->nrecmema);
pci_read_config_word(pvt->branchmap_werrors,
- NRECMEMB, &info->nrecmemb);
+ NRECMEMB, &info->nrecmemb);
/* Clear the error bits, by writing them back */
pci_write_config_dword(pvt->branchmap_werrors,
- FERR_FAT_FBD, value);
+ FERR_FAT_FBD, value);
} else {
info->ferr_fat_fbd = 0;
info->nerr_fat_fbd = 0;
/* harvest the various error data we need */
pci_read_config_dword(pvt->branchmap_werrors,
- NERR_NF_FBD, &info->nerr_nf_fbd);
+ NERR_NF_FBD, &info->nerr_nf_fbd);
pci_read_config_word(pvt->branchmap_werrors,
- RECMEMA, &info->recmema);
+ RECMEMA, &info->recmema);
pci_read_config_dword(pvt->branchmap_werrors,
- RECMEMB, &info->recmemb);
+ RECMEMB, &info->recmemb);
pci_read_config_dword(pvt->branchmap_werrors,
- REDMEMB, &info->redmemb);
+ REDMEMB, &info->redmemb);
/* Clear the error bits, by writing them back */
pci_write_config_dword(pvt->branchmap_werrors,
- FERR_NF_FBD, value);
+ FERR_NF_FBD, value);
} else {
info->ferr_nf_fbd = 0;
info->nerr_nf_fbd = 0;
}
}
-/******************************************************************************
+/*
* i5000_process_fatal_error_info(struct mem_ctl_info *mci,
* struct i5000_error_info *info,
* int handle_errors);
* handle the Intel FATAL errors, if any
*/
static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
- struct i5000_error_info * info,
- int handle_errors)
+ struct i5000_error_info *info,
+ int handle_errors)
{
char msg[EDAC_MC_LABEL_LEN + 1 + 90];
u32 allErrors;
edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
}
-/******************************************************************************
+/*
* i5000_process_fatal_error_info(struct mem_ctl_info *mci,
- * struct i5000_error_info *info,
- * int handle_errors);
+ * struct i5000_error_info *info,
+ * int handle_errors);
*
* handle the Intel NON-FATAL errors, if any
*/
static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
- struct i5000_error_info * info,
- int handle_errors)
+ struct i5000_error_info *info,
+ int handle_errors)
{
char msg[EDAC_MC_LABEL_LEN + 1 + 90];
u32 allErrors;
cas = NREC_CAS(info->nrecmemb);
debugf0
- ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
- "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
- rank, channel, channel + 1, branch >> 1, bank,
- rdwr ? "Write" : "Read", ras, cas);
+ ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
+ "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
+ rank, channel, channel + 1, branch >> 1, bank,
+ rdwr ? "Write" : "Read", ras, cas);
/* Form out message */
snprintf(msg, sizeof(msg),
misc_errors = allErrors & FERR_NF_THERMAL;
if (misc_errors) {
i5000_printk(KERN_WARNING, "\tTHERMAL Error, bits= 0x%x\n",
- misc_errors);
+ misc_errors);
}
/* See if any of the thermal errors have fired */
misc_errors = allErrors & FERR_NF_NON_RETRY;
if (misc_errors) {
i5000_printk(KERN_WARNING, "\tNON-Retry Errors, bits= 0x%x\n",
- misc_errors);
+ misc_errors);
}
/* See if any of the thermal errors have fired */
misc_errors = allErrors & FERR_NF_NORTH_CRC;
if (misc_errors) {
i5000_printk(KERN_WARNING,
- "\tNORTHBOUND CRC Error, bits= 0x%x\n",
- misc_errors);
+ "\tNORTHBOUND CRC Error, bits= 0x%x\n",
+ misc_errors);
}
/* See if any of the thermal errors have fired */
misc_errors = allErrors & FERR_NF_SPD_PROTOCOL;
if (misc_errors) {
i5000_printk(KERN_WARNING,
- "\tSPD Protocol Error, bits= 0x%x\n",
- misc_errors);
+ "\tSPD Protocol Error, bits= 0x%x\n",
+ misc_errors);
}
/* See if any of the thermal errors have fired */
misc_errors = allErrors & FERR_NF_DIMM_SPARE;
if (misc_errors) {
i5000_printk(KERN_WARNING, "\tDIMM-Spare Error, bits= 0x%x\n",
- misc_errors);
+ misc_errors);
}
}
-/******************************************************************************
+/*
* i5000_process_error_info Process the error info that is
* in the 'info' structure, previously retrieved from hardware
*/
static void i5000_process_error_info(struct mem_ctl_info *mci,
- struct i5000_error_info * info,
- int handle_errors)
+ struct i5000_error_info *info,
+ int handle_errors)
{
/* First handle any fatal errors that occurred */
i5000_process_fatal_error_info(mci, info, handle_errors);
i5000_process_nonfatal_error_info(mci, info, handle_errors);
}
-/******************************************************************************
+/*
* i5000_clear_error Retrieve any error from the hardware
* but do NOT process that error.
* Used for 'clearing' out of previous errors
i5000_get_error_info(mci, &info);
}
-/******************************************************************************
+/*
* i5000_check_error Retrieve and process errors reported by the
* hardware. Called by the Core module.
*/
i5000_process_error_info(mci, &info, 1);
}
-/******************************************************************************
+/*
* i5000_get_devices Find and perform 'get' operation on the MCH's
* device/functions we want to reference for this driver
*
struct i5000_pvt *pvt;
struct pci_dev *pdev;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
/* Attempt to 'get' the MCH register we want */
pdev = NULL;
while (1) {
pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
+ PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
/* End of list, leave */
if (pdev == NULL) {
i5000_printk(KERN_ERR,
- "'system address,Process Bus' "
- "device not found:"
- "vendor 0x%x device 0x%x FUNC 1 "
- "(broken BIOS?)\n",
- PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_I5000_DEV16);
+ "'system address,Process Bus' "
+ "device not found:"
+ "vendor 0x%x device 0x%x FUNC 1 "
+ "(broken BIOS?)\n",
+ PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_I5000_DEV16);
return 1;
}
pdev = NULL;
while (1) {
pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
+ PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
if (pdev == NULL) {
i5000_printk(KERN_ERR,
- "MC: 'branchmap,control,errors' "
- "device not found:"
- "vendor 0x%x device 0x%x Func 2 "
- "(broken BIOS?)\n",
- PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_I5000_DEV16);
+ "MC: 'branchmap,control,errors' "
+ "device not found:"
+ "vendor 0x%x device 0x%x Func 2 "
+ "(broken BIOS?)\n",
+ PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_I5000_DEV16);
pci_dev_put(pvt->branchmap_werrors);
return 1;
pdev = NULL;
pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
+ PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
if (pdev == NULL) {
i5000_printk(KERN_ERR,
- "MC: 'BRANCH 0' device not found:"
- "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
- PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
+ "MC: 'BRANCH 0' device not found:"
+ "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
+ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
pci_dev_put(pvt->branchmap_werrors);
pci_dev_put(pvt->fsb_error_regs);
if (pvt->maxch >= CHANNELS_PER_BRANCH) {
pdev = NULL;
pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
+ PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
if (pdev == NULL) {
i5000_printk(KERN_ERR,
- "MC: 'BRANCH 1' device not found:"
- "vendor 0x%x device 0x%x Func 0 "
- "(broken BIOS?)\n",
- PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_I5000_BRANCH_1);
+ "MC: 'BRANCH 1' device not found:"
+ "vendor 0x%x device 0x%x Func 0 "
+ "(broken BIOS?)\n",
+ PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_I5000_BRANCH_1);
pci_dev_put(pvt->branchmap_werrors);
pci_dev_put(pvt->fsb_error_regs);
return 0;
}
-/******************************************************************************
+/*
* i5000_put_devices 'put' all the devices that we have
* reserved via 'get'
*/
{
struct i5000_pvt *pvt;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
pci_dev_put(pvt->branch_0); /* DEV 21 */
/* Only if more than 2 channels do we release the second branch */
- if (pvt->maxch >= CHANNELS_PER_BRANCH) {
+ if (pvt->maxch >= CHANNELS_PER_BRANCH)
pci_dev_put(pvt->branch_1); /* DEV 22 */
- }
}
-/******************************************************************************
+/*
* determine_amb_resent
*
* the information is contained in NUM_MTRS different registers
return amb_present;
}
-/******************************************************************************
+/*
* determine_mtr(pvt, csrow, channel)
*
* return the proper MTR register as determine by the csrow and channel desired
return mtr;
}
-/******************************************************************************
+/*
*/
static void decode_mtr(int slot_row, u16 mtr)
{
}
static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
- struct i5000_dimm_info *dinfo)
+ struct i5000_dimm_info *dinfo)
{
int mtr;
int amb_present_reg;
dinfo->dual_rank = MTR_DIMM_RANK(mtr);
if (!((dinfo->dual_rank == 0) &&
- ((csrow & 0x1) == 0x1))) {
+ ((csrow & 0x1) == 0x1))) {
/* Start with the number of bits for a Bank
* on the DRAM */
addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
}
}
-/******************************************************************************
+/*
* calculate_dimm_size
*
* also will output a DIMM matrix map, if debug is enabled, for viewing
mem_buffer = p = kmalloc(space, GFP_KERNEL);
if (p == NULL) {
i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
- __FILE__, __func__);
+ __FILE__, __func__);
return;
}
* then reset the message buffer */
if (csrow & 0x1) {
n = snprintf(p, space, "---------------------------"
- "--------------------------------");
+ "--------------------------------");
p += n;
space -= n;
debugf2("%s\n", mem_buffer);
/* Output the last bottom 'boundary' marker */
n = snprintf(p, space, "---------------------------"
- "--------------------------------\n");
+ "--------------------------------\n");
p += n;
space -= n;
kfree(mem_buffer);
}
-/******************************************************************************
+/*
* i5000_get_mc_regs read in the necessary registers and
* cache locally
*
int maxdimmperch;
int way0, way1;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
pci_read_config_dword(pvt->system_address, AMBASE,
- (u32 *) & pvt->ambase);
+ (u32 *) & pvt->ambase);
pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
- ((u32 *) & pvt->ambase) + sizeof(u32));
+ ((u32 *) & pvt->ambase) + sizeof(u32));
maxdimmperch = pvt->maxdimmperch;
maxch = pvt->maxch;
int where = MTR0 + (slot_row * sizeof(u32));
pci_read_config_word(pvt->branch_0, where,
- &pvt->b0_mtr[slot_row]);
+ &pvt->b0_mtr[slot_row]);
debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
pvt->b0_mtr[slot_row]);
if (pvt->maxch >= CHANNELS_PER_BRANCH) {
pci_read_config_word(pvt->branch_1, where,
- &pvt->b1_mtr[slot_row]);
+ &pvt->b1_mtr[slot_row]);
debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
where, pvt->b0_mtr[slot_row]);
} else {
decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
}
pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
- &pvt->b0_ambpresent0);
+ &pvt->b0_ambpresent0);
debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
- &pvt->b0_ambpresent1);
+ &pvt->b0_ambpresent1);
debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
/* Only if we have 2 branchs (4 channels) */
decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
}
pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
- &pvt->b1_ambpresent0);
+ &pvt->b1_ambpresent0);
debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
pvt->b1_ambpresent0);
pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
- &pvt->b1_ambpresent1);
+ &pvt->b1_ambpresent1);
debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
pvt->b1_ambpresent1);
}
calculate_dimm_size(pvt);
}
-/******************************************************************************
+/*
* i5000_init_csrows Initialize the 'csrows' table within
* the mci control structure with the
* addressing of memory.
int channel;
int csrow;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
channel_count = pvt->maxch;
max_csrows = pvt->maxdimmperch * 2;
return empty;
}
-/******************************************************************************
+/*
* i5000_enable_error_reporting
* Turn on the memory reporting features of the hardware
*/
struct i5000_pvt *pvt;
u32 fbd_error_mask;
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
/* Read the FBD Error Mask Register */
pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
- &fbd_error_mask);
+ &fbd_error_mask);
/* Enable with a '0' */
fbd_error_mask &= ~(ENABLE_EMASK_ALL);
pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
- fbd_error_mask);
+ fbd_error_mask);
}
-/******************************************************************************
+/*
* i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
*
* ask the device how many channels are present and how many CSROWS
* as well
*/
static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
- int *num_dimms_per_channel,
- int *num_channels)
+ int *num_dimms_per_channel,
+ int *num_channels)
{
u8 value;
*num_channels = (int)value;
}
-/******************************************************************************
+/*
* i5000_probe1 Probe for ONE instance of device to see if it is
* present.
* return:
return -ENODEV;
/* make sure error reporting method is sane */
- switch(edac_op_state) {
- case EDAC_OPSTATE_POLL:
- case EDAC_OPSTATE_NMI:
- break;
- default:
- edac_op_state = EDAC_OPSTATE_POLL;
- break;
+ switch (edac_op_state) {
+ case EDAC_OPSTATE_POLL:
+ case EDAC_OPSTATE_NMI:
+ break;
+ default:
+ edac_op_state = EDAC_OPSTATE_POLL;
+ break;
}
/* Ask the devices for the number of CSROWS and CHANNELS so
* some fancy mobo determination.
*/
i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
- &num_channels);
+ &num_channels);
num_csrows = num_dimms_per_channel * 2;
debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
__func__, num_channels, num_dimms_per_channel, num_csrows);
/* allocate a new MC control structure */
- mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels);
+ mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
if (mci == NULL)
return -ENOMEM;
mci->dev = &pdev->dev; /* record ptr to the generic device */
- pvt = (struct i5000_pvt *)mci->pvt_info;
+ pvt = mci->pvt_info;
pvt->system_address = pdev; /* Record this device in our private */
pvt->maxch = num_channels;
pvt->maxdimmperch = num_dimms_per_channel;
}
/* add this new MC control structure to EDAC's list of MCs */
- if (edac_mc_add_mc(mci, pvt->node_id)) {
+ if (edac_mc_add_mc(mci)) {
debugf0("MC: " __FILE__
": %s(): failed edac_mc_add_mc()\n", __func__);
/* FIXME: perhaps some code should go here that disables error
i5000_clear_error(mci);
+ /* allocating generic PCI control info */
+ i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
+ if (!i5000_pci) {
+ printk(KERN_WARNING
+ "%s(): Unable to create PCI control\n",
+ __func__);
+ printk(KERN_WARNING
+ "%s(): PCI error report via EDAC not setup\n",
+ __func__);
+ }
+
return 0;
/* Error exit unwinding stack */
- fail1:
+fail1:
i5000_put_devices(mci);
- fail0:
+fail0:
edac_mc_free(mci);
return -ENODEV;
}
-/******************************************************************************
+/*
* i5000_init_one constructor for one instance of device
*
* returns:
* count (>= 0)
*/
static int __devinit i5000_init_one(struct pci_dev *pdev,
- const struct pci_device_id *id)
+ const struct pci_device_id *id)
{
int rc;
return i5000_probe1(pdev, id->driver_data);
}
-/**************************************************************************
+/*
* i5000_remove_one destructor for one instance of device
*
*/
debugf0(__FILE__ ": %s()\n", __func__);
+ if (i5000_pci)
+ edac_pci_release_generic_ctl(i5000_pci);
+
if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
return;
edac_mc_free(mci);
}
-/**************************************************************************
+/*
* pci_device_id table for which devices we are looking for
*
* The "E500P" device is the first device supported.
MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
-/**************************************************************************
+/*
* i5000_driver pci_driver structure for this module
*
*/
static struct pci_driver i5000_driver = {
- .name = __stringify(KBUILD_BASENAME),
+ .name = KBUILD_BASENAME,
.probe = i5000_init_one,
.remove = __devexit_p(i5000_remove_one),
.id_table = i5000_pci_tbl,
};
-/**************************************************************************
+/*
* i5000_init Module entry function
* Try to initialize this module for its devices
*/
return (pci_rc < 0) ? pci_rc : 0;
}
-/**************************************************************************
+/*
* i5000_exit() Module exit function
* Unregister the driver
*/
MODULE_AUTHOR
("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
- I5000_REVISION);
+ I5000_REVISION);
module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
git.openpandora.org / pandora-kernel.git / blobdiff