int i;
for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
- int hw_counter = i % NUM_COUNTERS;
+ int hw_counter = op_x86_virt_to_phys(i);
if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
else
/* setup reset_value */
for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
- if (counter_config[i].enabled) {
+ if (counter_config[i].enabled)
reset_value[i] = counter_config[i].count;
- } else {
+ else
reset_value[i] = 0;
- }
}
/* clear all counters */
#ifdef CONFIG_OPROFILE_IBS
-static inline int
+static inline void
op_amd_handle_ibs(struct pt_regs * const regs,
struct op_msrs const * const msrs)
{
struct op_entry entry;
if (!has_ibs)
- return 0;
+ return;
if (ibs_config.fetch_enabled) {
rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
}
}
-
- return 1;
}
static inline void op_amd_start_ibs(void)
#else
-static inline int op_amd_handle_ibs(struct pt_regs * const regs,
- struct op_msrs const * const msrs)
-{
- return 0;
-}
+static inline void op_amd_handle_ibs(struct pt_regs * const regs,
+ struct op_msrs const * const msrs) { }
static inline void op_amd_start_ibs(void) { }
static inline void op_amd_stop_ibs(void) { }
#endif /* CONFIG_OPROFILE_IBS */
-struct op_x86_model_spec const op_amd_spec = {
+struct op_x86_model_spec op_amd_spec = {
.num_counters = NUM_COUNTERS,
.num_controls = NUM_CONTROLS,
.num_virt_counters = NUM_VIRT_COUNTERS,
- .num_virt_controls = NUM_VIRT_CONTROLS,
.reserved = MSR_AMD_EVENTSEL_RESERVED,
.event_mask = OP_EVENT_MASK,
.init = op_amd_init,