Merge branch 'bkl-removal' into next

[pandora-kernel.git] / arch / x86 / kernel / head_64.S

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 263b9d1..b07ac7b 100644 (file)
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -32,6 +32,13 @@
  *
  */
 
+#define pud_index(x)   (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+
+L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
+L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
+L4_START_KERNEL = pgd_index(__START_KERNEL_map)
+L3_START_KERNEL = pud_index(__START_KERNEL_map)
+
        .text
        .section .text.head
        .code64
@@ -77,8 +84,8 @@ startup_64:
        /* Fixup the physical addresses in the page table
         */
        addq    %rbp, init_level4_pgt + 0(%rip)
-       addq    %rbp, init_level4_pgt + (258*8)(%rip)
-       addq    %rbp, init_level4_pgt + (511*8)(%rip)
+       addq    %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
+       addq    %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
 
        addq    %rbp, level3_ident_pgt + 0(%rip)
 
@@ -191,7 +198,7 @@ ENTRY(secondary_startup_64)
        movq    %rax, %cr0
 
        /* Setup a boot time stack */
-       movq init_rsp(%rip),%rsp
+       movq stack_start(%rip),%rsp
 
        /* zero EFLAGS after setting rsp */
        pushq $0
@@ -203,7 +210,7 @@ ENTRY(secondary_startup_64)
         * addresses where we're currently running on. We have to do that here
         * because in 32bit we couldn't load a 64bit linear address.
         */
-       lgdt    cpu_gdt_descr(%rip)
+       lgdt    early_gdt_descr(%rip)
 
        /* set up data segments. actually 0 would do too */
        movl $__KERNEL_DS,%eax
@@ -252,8 +259,9 @@ ENTRY(secondary_startup_64)
        .quad   x86_64_start_kernel
        __FINITDATA
 
-       ENTRY(init_rsp)
+       ENTRY(stack_start)
        .quad  init_thread_union+THREAD_SIZE-8
+       .word  0
 
 bad_address:
        jmp bad_address
@@ -337,9 +345,9 @@ ENTRY(name)
         */
 NEXT_PAGE(init_level4_pgt)
        .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-       .fill   257,8,0
+       .org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
        .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-       .fill   252,8,0
+       .org    init_level4_pgt + L4_START_KERNEL*8, 0
        /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
        .quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
 
@@ -348,7 +356,7 @@ NEXT_PAGE(level3_ident_pgt)
        .fill   511,8,0
 
 NEXT_PAGE(level3_kernel_pgt)
-       .fill   510,8,0
+       .fill   L3_START_KERNEL,8,0
        /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
        .quad   level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
        .quad   level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
@@ -379,7 +387,7 @@ NEXT_PAGE(level2_kernel_pgt)
         *  If you want to increase this then increase MODULES_VADDR
         *  too.)
         */
-       PMDS(0, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL,
+       PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
                KERNEL_IMAGE_SIZE/PMD_SIZE)
 
 NEXT_PAGE(level2_spare_pgt)
@@ -390,54 +398,16 @@ NEXT_PAGE(level2_spare_pgt)
 
        .data
        .align 16
-       .globl cpu_gdt_descr
-cpu_gdt_descr:
-       .word   gdt_end-cpu_gdt_table-1
-gdt:
-       .quad   cpu_gdt_table
-#ifdef CONFIG_SMP
-       .rept   NR_CPUS-1
-       .word   0
-       .quad   0
-       .endr
-#endif
+       .globl early_gdt_descr
+early_gdt_descr:
+       .word   GDT_ENTRIES*8-1
+       .quad   per_cpu__gdt_page
 
 ENTRY(phys_base)
        /* This must match the first entry in level2_kernel_pgt */
        .quad   0x0000000000000000
 
-/* We need valid kernel segments for data and code in long mode too
- * IRET will check the segment types  kkeil 2000/10/28
- * Also sysret mandates a special GDT layout 
- */
-                               
-       .section .data.page_aligned, "aw"
-       .align PAGE_SIZE
-
-/* The TLS descriptors are currently at a different place compared to i386.
-   Hopefully nobody expects them at a fixed place (Wine?) */
        
-ENTRY(cpu_gdt_table)
-       .quad   0x0000000000000000      /* NULL descriptor */
-       .quad   0x00cf9b000000ffff      /* __KERNEL32_CS */
-       .quad   0x00af9b000000ffff      /* __KERNEL_CS */
-       .quad   0x00cf93000000ffff      /* __KERNEL_DS */
-       .quad   0x00cffb000000ffff      /* __USER32_CS */
-       .quad   0x00cff3000000ffff      /* __USER_DS, __USER32_DS  */
-       .quad   0x00affb000000ffff      /* __USER_CS */
-       .quad   0x0                     /* unused */
-       .quad   0,0                     /* TSS */
-       .quad   0,0                     /* LDT */
-       .quad   0,0,0                   /* three TLS descriptors */ 
-       .quad   0x0000f40000000000      /* node/CPU stored in limit */
-gdt_end:       
-       /* asm/segment.h:GDT_ENTRIES must match this */ 
-       /* This should be a multiple of the cache line size */
-       /* GDTs of other CPUs are now dynamically allocated */
-
-       /* zero the remaining page */
-       .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
-
        .section .bss, "aw", @nobits
        .align L1_CACHE_BYTES
 ENTRY(idt_table)