x86-64: Improve insn scheduling in SAVE_ARGS_IRQ

[pandora-kernel.git] / arch / x86 / kernel / entry_64.S

diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index a20e1cb..211b2e1 100644 (file)
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -319,7 +319,7 @@ ENDPROC(native_usergs_sysret64)
        movq %rsp, %rsi
 
        leaq -RBP(%rsp),%rdi    /* arg1 for handler */
-       testl $3, CS(%rdi)
+       testl $3, CS-RBP(%rsi)
        je 1f
        SWAPGS
        /*
@@ -329,11 +329,10 @@ ENDPROC(native_usergs_sysret64)
         * moving irq_enter into assembly, which would be too much work)
         */
 1:     incl PER_CPU_VAR(irq_count)
-       jne 2f
-       mov PER_CPU_VAR(irq_stack_ptr),%rsp
+       cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp
        CFI_DEF_CFA_REGISTER    rsi
 
-2:     /* Store previous stack value */
+       /* Store previous stack value */
        pushq %rsi
        CFI_ESCAPE      0x0f /* DW_CFA_def_cfa_expression */, 6, \
                        0x77 /* DW_OP_breg7 */, 0, \