x86, amd: Avoid cache aliasing penalties on AMD family 15h

[pandora-kernel.git] / arch / x86 / kernel / cpu / amd.c

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8f5cabb..b0234bc 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -458,6 +458,19 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
                                        "with P0 frequency!\n");
                }
        }
+
+       if (c->x86 == 0x15) {
+               unsigned long upperbit;
+               u32 cpuid, assoc;
+
+               cpuid    = cpuid_edx(0x80000005);
+               assoc    = cpuid >> 16 & 0xff;
+               upperbit = ((cpuid >> 24) << 10) / assoc;
+
+               va_align.mask     = (upperbit - 1) & PAGE_MASK;
+               va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
+
+       }
 }
 
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
@@ -612,8 +625,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        }
 #endif
 
-       /* As a rule processors have APIC timer running in deep C states */
-       if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400))
+       /*
+        * Family 0x12 and above processors have APIC timer
+        * running in deep C states.
+        */
+       if (c->x86 > 0x11)
                set_cpu_cap(c, X86_FEATURE_ARAT);
 
        /*