x86, ticketlock: remove obsolete comment

[pandora-kernel.git] / arch / x86 / include / asm / spinlock.h

diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index ea2a04f..972c260 100644 (file)
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -49,105 +49,49 @@
  * issues and should be optimal for the uncontended case. Note the tail must be
  * in the high part, because a wide xadd increment of the low part would carry
  * up and contaminate the high part.
- *
- * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
- * save some instructions and make the code more elegant. There really isn't
- * much between them in performance though, especially as locks are out of line.
  */
-#if (NR_CPUS < 256)
 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
 {
-       unsigned short inc = 1 << TICKET_SHIFT;
-
-       asm volatile (
-               LOCK_PREFIX "xaddw %w0, %1\n"
-               "1:\t"
-               "cmpb %h0, %b0\n\t"
-               "je 2f\n\t"
-               "rep ; nop\n\t"
-               "movb %1, %b0\n\t"
-               /* don't need lfence here, because loads are in-order */
-               "jmp 1b\n"
-               "2:"
-               : "+Q" (inc), "+m" (lock->slock)
-               :
-               : "memory", "cc");
+       register struct __raw_tickets inc = { .tail = 1 };
+
+       inc = xadd(&lock->tickets, inc);
+
+       for (;;) {
+               if (inc.head == inc.tail)
+                       break;
+               cpu_relax();
+               inc.head = ACCESS_ONCE(lock->tickets.head);
+       }
+       barrier();              /* make sure nothing creeps before the lock is taken */
 }
 
 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
 {
-       unsigned int tmp, new;
-
-       asm volatile("movzwl %2, %0\n\t"
-                    "cmpb %h0,%b0\n\t"
-                    "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
-                    "jne 1f\n\t"
-                    LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
-                    "1:"
-                    "sete %b1\n\t"
-                    "movzbl %b1,%0\n\t"
-                    : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
-                    :
-                    : "memory", "cc");
+       arch_spinlock_t old, new;
+
+       old.tickets = ACCESS_ONCE(lock->tickets);
+       if (old.tickets.head != old.tickets.tail)
+               return 0;
+
+       new.head_tail = old.head_tail + (1 << TICKET_SHIFT);
 
-       return tmp;
+       /* cmpxchg is a full barrier, so nothing can move before it */
+       return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail;
 }
 
+#if (NR_CPUS < 256)
 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
        asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
-                    : "+m" (lock->slock)
+                    : "+m" (lock->head_tail)
                     :
                     : "memory", "cc");
 }
 #else
-static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock)
-{
-       unsigned inc = 1 << TICKET_SHIFT;
-       unsigned tmp;
-
-       asm volatile(LOCK_PREFIX "xaddl %0, %1\n"
-                    "movzwl %w0, %2\n\t"
-                    "shrl $16, %0\n\t"
-                    "1:\t"
-                    "cmpl %0, %2\n\t"
-                    "je 2f\n\t"
-                    "rep ; nop\n\t"
-                    "movzwl %1, %2\n\t"
-                    /* don't need lfence here, because loads are in-order */
-                    "jmp 1b\n"
-                    "2:"
-                    : "+r" (inc), "+m" (lock->slock), "=&r" (tmp)
-                    :
-                    : "memory", "cc");
-}
-
-static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
-{
-       unsigned tmp;
-       unsigned new;
-
-       asm volatile("movl %2,%0\n\t"
-                    "movl %0,%1\n\t"
-                    "roll $16, %0\n\t"
-                    "cmpl %0,%1\n\t"
-                    "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
-                    "jne 1f\n\t"
-                    LOCK_PREFIX "cmpxchgl %1,%2\n\t"
-                    "1:"
-                    "sete %b1\n\t"
-                    "movzbl %b1,%0\n\t"
-                    : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
-                    :
-                    : "memory", "cc");
-
-       return tmp;
-}
-
 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock)
 {
        asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
-                    : "+m" (lock->slock)
+                    : "+m" (lock->head_tail)
                     :
                     : "memory", "cc");
 }