Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

[pandora-kernel.git] / arch / sparc64 / mm / ultra.S

diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 796e005..4c8ca13 100644 (file)
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -1,7 +1,7 @@
-/* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $
+/*
  * ultra.S: Don't expand these all over the place...
  *
- * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com)
+ * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
  */
 
 #include <asm/asi.h>
@@ -15,6 +15,7 @@
 #include <asm/thread_info.h>
 #include <asm/cacheflush.h>
 #include <asm/hypervisor.h>
+#include <asm/cpudata.h>
 
        /* Basically, most of the Spitfire vs. Cheetah madness
         * has to do with the fact that Cheetah does not support
@@ -514,6 +515,32 @@ xcall_report_regs:
        b               rtrap_xcall
         ldx            [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 
+#ifdef CONFIG_MAGIC_SYSRQ
+       .globl          xcall_fetch_glob_regs
+xcall_fetch_glob_regs:
+       sethi           %hi(global_reg_snapshot), %g1
+       or              %g1, %lo(global_reg_snapshot), %g1
+       __GET_CPUID(%g2)
+       sllx            %g2, 6, %g3
+       add             %g1, %g3, %g1
+       rdpr            %tstate, %g7
+       stx             %g7, [%g1 + GR_SNAP_TSTATE]
+       rdpr            %tpc, %g7
+       stx             %g7, [%g1 + GR_SNAP_TPC]
+       rdpr            %tnpc, %g7
+       stx             %g7, [%g1 + GR_SNAP_TNPC]
+       stx             %o7, [%g1 + GR_SNAP_O7]
+       stx             %i7, [%g1 + GR_SNAP_I7]
+       sethi           %hi(trap_block), %g7
+       or              %g7, %lo(trap_block), %g7
+       sllx            %g2, TRAP_BLOCK_SZ_SHIFT, %g2
+       add             %g7, %g2, %g7
+       ldx             [%g7 + TRAP_PER_CPU_THREAD], %g3
+       membar          #StoreStore
+       stx             %g3, [%g1 + GR_SNAP_THREAD]
+       retry
+#endif /* CONFIG_MAGIC_SYSRQ */
+
 #ifdef DCACHE_ALIASING_POSSIBLE
        .align          32
        .globl          xcall_flush_dcache_page_cheetah
@@ -661,6 +688,11 @@ xcall_call_function:
        wr              %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
        retry
 
+       .globl          xcall_call_function_single
+xcall_call_function_single:
+       wr              %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
+       retry
+
        .globl          xcall_receive_signal
 xcall_receive_signal:
        wr              %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint