u16 tmp16;
u8 tmp8;
+ if (bus_dev == pbm->pci_bus && devfn == 0x00)
+ return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
+ size, value);
switch (size) {
case 1:
*value = 0xff;
unsigned char bus = bus_dev->number;
u32 *addr;
+ if (bus_dev == pbm->pci_bus && devfn == 0x00)
+ return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
+ size, value);
addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
if (!addr)
return PCIBIOS_SUCCESSFUL;
static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
enum schizo_error_type type)
{
- struct pci_strbuf *strbuf = &pbm->stc;
+ struct strbuf *strbuf = &pbm->stc;
unsigned long regbase = pbm->pbm_regs;
unsigned long err_base, tag_base, line_base;
u64 control;
static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
enum schizo_error_type type)
{
- struct pci_iommu *iommu = pbm->iommu;
+ struct iommu *iommu = pbm->iommu;
unsigned long iommu_tag[16];
unsigned long iommu_data[16];
unsigned long flags;
schizo_register_error_handlers(p);
}
-static void schizo_base_address_update(struct pci_dev *pdev, int resource)
-{
- struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
- struct resource *res, *root;
- u32 reg;
- int where, size, is_64bit;
-
- res = &pdev->resource[resource];
- if (resource < 6) {
- where = PCI_BASE_ADDRESS_0 + (resource * 4);
- } else if (resource == PCI_ROM_RESOURCE) {
- where = pdev->rom_base_reg;
- } else {
- /* Somebody might have asked allocation of a non-standard resource */
- return;
- }
-
- is_64bit = 0;
- if (res->flags & IORESOURCE_IO)
- root = &pbm->io_space;
- else {
- root = &pbm->mem_space;
- if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
- == PCI_BASE_ADDRESS_MEM_TYPE_64)
- is_64bit = 1;
- }
-
- size = res->end - res->start;
- pci_read_config_dword(pdev, where, ®);
- reg = ((reg & size) |
- (((u32)(res->start - root->start)) & ~size));
- if (resource == PCI_ROM_RESOURCE) {
- reg |= PCI_ROM_ADDRESS_ENABLE;
- res->flags |= IORESOURCE_ROM_ENABLE;
- }
- pci_write_config_dword(pdev, where, reg);
-
- /* This knows that the upper 32-bits of the address
- * must be zero. Our PCI common layer enforces this.
- */
- if (is_64bit)
- pci_write_config_dword(pdev, where + 4, 0);
-}
-
-static void schizo_resource_adjust(struct pci_dev *pdev,
- struct resource *res,
- struct resource *root)
-{
- res->start += root->start;
- res->end += root->start;
-}
-
#define SCHIZO_STRBUF_CONTROL (0x02800UL)
#define SCHIZO_STRBUF_FLUSH (0x02808UL)
#define SCHIZO_STRBUF_FSYNC (0x02810UL)
static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
{
- struct pci_iommu *iommu = pbm->iommu;
+ struct iommu *iommu = pbm->iommu;
unsigned long i, tagbase, database;
struct property *prop;
u32 vdma[2], dma_mask;
struct device_node *dp, u32 portid,
int chip_type)
{
- struct linux_prom64_registers *regs;
- unsigned int *busrange;
+ const struct linux_prom64_registers *regs;
+ const unsigned int *busrange;
struct pci_pbm_info *pbm;
const char *chipset_name;
- u32 *ino_bitmap;
+ const u32 *ino_bitmap;
int is_pbm_a;
switch (chip_type) {
pbm->portid = portid;
pbm->parent = p;
pbm->prom_node = dp;
- pbm->pci_first_slot = 1;
pbm->chip_type = chip_type;
pbm->chip_version = of_getintprop_default(dp, "version#", 0);
static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
{
struct pci_controller_info *p;
- struct pci_iommu *iommu;
+ struct iommu *iommu;
u32 portid;
portid = of_getintprop_default(dp, "portid", 0xff);
if (!p)
goto memfail;
- iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
+ iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
if (!iommu)
goto memfail;
p->pbm_A.iommu = iommu;
- iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
+ iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
if (!iommu)
goto memfail;
p->index = pci_num_controllers++;
p->scan_bus = schizo_scan_bus;
- p->base_address_update = schizo_base_address_update;
- p->resource_adjust = schizo_resource_adjust;
p->pci_ops = &schizo_ops;
/* Like PSYCHO we have a 2GB aligned area for memory space. */