#include <linux/seq_file.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/rwlock.h>
#include <asm/sizes.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
-static void pmb_unmap_entry(struct pmb_entry *);
+struct pmb_entry;
+struct pmb_entry {
+ unsigned long vpn;
+ unsigned long ppn;
+ unsigned long flags;
+ unsigned long size;
+
+ spinlock_t lock;
+
+ /*
+ * 0 .. NR_PMB_ENTRIES for specific entry selection, or
+ * PMB_NO_ENTRY to search for a free one
+ */
+ int entry;
+
+ /* Adjacent entry link for contiguous multi-entry mappings */
+ struct pmb_entry *link;
+};
+
+static void pmb_unmap_entry(struct pmb_entry *, int depth);
+
+static DEFINE_RWLOCK(pmb_rwlock);
static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
static int pmb_alloc_entry(void)
{
- unsigned int pos;
+ int pos;
-repeat:
pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
-
- if (unlikely(pos > NR_PMB_ENTRIES))
- return -ENOSPC;
-
- if (test_and_set_bit(pos, pmb_map))
- goto repeat;
+ if (pos >= 0 && pos < NR_PMB_ENTRIES)
+ __set_bit(pos, pmb_map);
+ else
+ pos = -ENOSPC;
return pos;
}
unsigned long flags, int entry)
{
struct pmb_entry *pmbe;
+ unsigned long irqflags;
+ void *ret = NULL;
int pos;
+ write_lock_irqsave(&pmb_rwlock, irqflags);
+
if (entry == PMB_NO_ENTRY) {
pos = pmb_alloc_entry();
- if (pos < 0)
- return ERR_PTR(pos);
+ if (unlikely(pos < 0)) {
+ ret = ERR_PTR(pos);
+ goto out;
+ }
} else {
- if (test_and_set_bit(entry, pmb_map))
- return ERR_PTR(-ENOSPC);
+ if (__test_and_set_bit(entry, pmb_map)) {
+ ret = ERR_PTR(-ENOSPC);
+ goto out;
+ }
+
pos = entry;
}
+ write_unlock_irqrestore(&pmb_rwlock, irqflags);
+
pmbe = &pmb_entry_list[pos];
- if (!pmbe)
- return ERR_PTR(-ENOMEM);
+
+ memset(pmbe, 0, sizeof(struct pmb_entry));
+
+ spin_lock_init(&pmbe->lock);
pmbe->vpn = vpn;
pmbe->ppn = ppn;
pmbe->flags = flags;
pmbe->entry = pos;
- pmbe->size = 0;
return pmbe;
+
+out:
+ write_unlock_irqrestore(&pmb_rwlock, irqflags);
+ return ret;
}
static void pmb_free(struct pmb_entry *pmbe)
{
- clear_bit(pmbe->entry, pmb_map);
- pmbe->entry = PMB_NO_ENTRY;
+ __clear_bit(pmbe->entry, pmb_map);
+
+ pmbe->entry = PMB_NO_ENTRY;
+ pmbe->link = NULL;
}
/*
- * Must be run uncached.
+ * Ensure that the PMB entries match our cache configuration.
+ *
+ * When we are in 32-bit address extended mode, CCR.CB becomes
+ * invalid, so care must be taken to manually adjust cacheable
+ * translations.
*/
-static void set_pmb_entry(struct pmb_entry *pmbe)
+static __always_inline unsigned long pmb_cache_flags(void)
{
- jump_to_uncached();
-
- __raw_writel(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
+ unsigned long flags = 0;
-#ifdef CONFIG_CACHE_WRITETHROUGH
- /*
- * When we are in 32-bit address extended mode, CCR.CB becomes
- * invalid, so care must be taken to manually adjust cacheable
- * translations.
- */
- if (likely(pmbe->flags & PMB_C))
- pmbe->flags |= PMB_WT;
+#if defined(CONFIG_CACHE_WRITETHROUGH)
+ flags |= PMB_C | PMB_WT | PMB_UB;
+#elif defined(CONFIG_CACHE_WRITEBACK)
+ flags |= PMB_C;
#endif
- __raw_writel(pmbe->ppn | pmbe->flags | PMB_V, mk_pmb_data(pmbe->entry));
+ return flags;
+}
- back_to_cached();
+/*
+ * Must be run uncached.
+ */
+static void __set_pmb_entry(struct pmb_entry *pmbe)
+{
+ writel_uncached(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
+ writel_uncached(pmbe->ppn | pmbe->flags | PMB_V,
+ mk_pmb_data(pmbe->entry));
}
-static void clear_pmb_entry(struct pmb_entry *pmbe)
+static void __clear_pmb_entry(struct pmb_entry *pmbe)
{
- unsigned int entry = pmbe->entry;
- unsigned long addr;
+ unsigned long addr, data;
+ unsigned long addr_val, data_val;
+
+ addr = mk_pmb_addr(pmbe->entry);
+ data = mk_pmb_data(pmbe->entry);
- jump_to_uncached();
+ addr_val = __raw_readl(addr);
+ data_val = __raw_readl(data);
/* Clear V-bit */
- addr = mk_pmb_addr(entry);
- __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
+ writel_uncached(addr_val & ~PMB_V, addr);
+ writel_uncached(data_val & ~PMB_V, data);
+}
- addr = mk_pmb_data(entry);
- __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
+static void set_pmb_entry(struct pmb_entry *pmbe)
+{
+ unsigned long flags;
- back_to_cached();
+ spin_lock_irqsave(&pmbe->lock, flags);
+ __set_pmb_entry(pmbe);
+ spin_unlock_irqrestore(&pmbe->lock, flags);
}
static struct {
flags = pgprot_val(prot);
+ pmb_flags = PMB_WT | PMB_UB;
+
/* Convert typical pgprot value to the PMB equivalent */
if (flags & _PAGE_CACHABLE) {
- if (flags & _PAGE_WT)
- pmb_flags = PMB_WT;
- else
- pmb_flags = PMB_C;
- } else
- pmb_flags = PMB_WT | PMB_UB;
+ pmb_flags |= PMB_C;
+
+ if ((flags & _PAGE_WT) == 0)
+ pmb_flags &= ~(PMB_WT | PMB_UB);
+ }
pmbp = NULL;
wanted = size;
again:
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
+ unsigned long flags;
+
if (size < pmb_sizes[i].size)
continue;
goto out;
}
- set_pmb_entry(pmbe);
+ spin_lock_irqsave(&pmbe->lock, flags);
+
+ __set_pmb_entry(pmbe);
phys += pmb_sizes[i].size;
vaddr += pmb_sizes[i].size;
* Link adjacent entries that span multiple PMB entries
* for easier tear-down.
*/
- if (likely(pmbp))
+ if (likely(pmbp)) {
+ spin_lock(&pmbp->lock);
pmbp->link = pmbe;
+ spin_unlock(&pmbp->lock);
+ }
pmbp = pmbe;
* pmb_sizes[i].size again.
*/
i--;
+
+ spin_unlock_irqrestore(&pmbe->lock, flags);
}
- if (size >= 0x1000000)
+ if (size >= SZ_16M)
goto again;
return wanted - size;
out:
- pmb_unmap_entry(pmbp);
+ pmb_unmap_entry(pmbp, NR_PMB_ENTRIES);
return err;
}
void pmb_unmap(unsigned long addr)
{
- struct pmb_entry *pmbe;
+ struct pmb_entry *pmbe = NULL;
int i;
+ read_lock(&pmb_rwlock);
+
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
if (test_bit(i, pmb_map)) {
pmbe = &pmb_entry_list[i];
- if (pmbe->vpn == addr) {
- pmb_unmap_entry(pmbe);
+ if (pmbe->vpn == addr)
break;
- }
}
}
+
+ read_unlock(&pmb_rwlock);
+
+ pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
}
-static void pmb_unmap_entry(struct pmb_entry *pmbe)
+static bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
{
- if (unlikely(!pmbe))
- return;
+ return (b->vpn == (a->vpn + a->size)) &&
+ (b->ppn == (a->ppn + a->size)) &&
+ (b->flags == a->flags);
+}
- if (!test_bit(pmbe->entry, pmb_map)) {
- WARN_ON(1);
- return;
- }
+static bool pmb_size_valid(unsigned long size)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
+ if (pmb_sizes[i].size == size)
+ return true;
+ return false;
+}
+
+static int pmb_size_to_flags(unsigned long size)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
+ if (pmb_sizes[i].size == size)
+ return pmb_sizes[i].flag;
+
+ return 0;
+}
+
+static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
+{
do {
struct pmb_entry *pmblink = pmbe;
* this entry in pmb_alloc() (even if we haven't filled
* it yet).
*
- * Therefore, calling clear_pmb_entry() is safe as no
+ * Therefore, calling __clear_pmb_entry() is safe as no
* other mapping can be using that slot.
*/
- clear_pmb_entry(pmbe);
+ __clear_pmb_entry(pmbe);
pmbe = pmblink->link;
pmb_free(pmblink);
- } while (pmbe);
+ } while (pmbe && --depth);
+}
+
+static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
+{
+ unsigned long flags;
+
+ if (unlikely(!pmbe))
+ return;
+
+ write_lock_irqsave(&pmb_rwlock, flags);
+ __pmb_unmap_entry(pmbe, depth);
+ write_unlock_irqrestore(&pmb_rwlock, flags);
}
static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
}
-static int pmb_synchronize_mappings(void)
+static void __init pmb_notify(void)
{
- unsigned int applied = 0;
- struct pmb_entry *pmbp = NULL;
- int i, j;
+ int i;
pr_info("PMB: boot mappings:\n");
+ read_lock(&pmb_rwlock);
+
+ for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+ struct pmb_entry *pmbe;
+
+ if (!test_bit(i, pmb_map))
+ continue;
+
+ pmbe = &pmb_entry_list[i];
+
+ pr_info(" 0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
+ pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
+ pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
+ }
+
+ read_unlock(&pmb_rwlock);
+}
+
+/*
+ * Sync our software copy of the PMB mappings with those in hardware. The
+ * mappings in the hardware PMB were either set up by the bootloader or
+ * very early on by the kernel.
+ */
+static void __init pmb_synchronize(void)
+{
+ struct pmb_entry *pmbp = NULL;
+ int i, j;
+
/*
* Run through the initial boot mappings, log the established
* ones, and blow away anything that falls outside of the valid
unsigned long addr, data;
unsigned long addr_val, data_val;
unsigned long ppn, vpn, flags;
+ unsigned long irqflags;
unsigned int size;
struct pmb_entry *pmbe;
/*
* Invalidate anything out of bounds.
*/
- __raw_writel(addr_val & ~PMB_V, addr);
- __raw_writel(data_val & ~PMB_V, data);
+ writel_uncached(addr_val & ~PMB_V, addr);
+ writel_uncached(data_val & ~PMB_V, data);
continue;
}
* Update the caching attributes if necessary
*/
if (data_val & PMB_C) {
-#if defined(CONFIG_CACHE_WRITETHROUGH)
- data_val |= PMB_WT;
-#elif defined(CONFIG_CACHE_WRITEBACK)
- data_val &= ~PMB_WT;
-#else
- data_val &= ~(PMB_C | PMB_WT);
-#endif
- __raw_writel(data_val, data);
+ data_val &= ~PMB_CACHE_MASK;
+ data_val |= pmb_cache_flags();
+
+ writel_uncached(data_val, data);
}
size = data_val & PMB_SZ_MASK;
continue;
}
+ spin_lock_irqsave(&pmbe->lock, irqflags);
+
for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
if (pmb_sizes[j].flag == size)
pmbe->size = pmb_sizes[j].size;
- /*
- * Compare the previous entry against the current one to
- * see if the entries span a contiguous mapping. If so,
- * setup the entry links accordingly.
- */
- if (pmbp && ((pmbe->vpn == (pmbp->vpn + pmbp->size)) &&
- (pmbe->ppn == (pmbp->ppn + pmbp->size))))
- pmbp->link = pmbe;
+ if (pmbp) {
+ spin_lock(&pmbp->lock);
+
+ /*
+ * Compare the previous entry against the current one to
+ * see if the entries span a contiguous mapping. If so,
+ * setup the entry links accordingly. Compound mappings
+ * are later coalesced.
+ */
+ if (pmb_can_merge(pmbp, pmbe))
+ pmbp->link = pmbe;
+
+ spin_unlock(&pmbp->lock);
+ }
pmbp = pmbe;
- pr_info("\t0x%08lx -> 0x%08lx [ %ldMB %scached ]\n",
- vpn >> PAGE_SHIFT, ppn >> PAGE_SHIFT, pmbe->size >> 20,
- (data_val & PMB_C) ? "" : "un");
+ spin_unlock_irqrestore(&pmbe->lock, irqflags);
+ }
+}
+
+static void __init pmb_merge(struct pmb_entry *head)
+{
+ unsigned long span, newsize;
+ struct pmb_entry *tail;
+ int i = 1, depth = 0;
+
+ span = newsize = head->size;
+
+ tail = head->link;
+ while (tail) {
+ span += tail->size;
+
+ if (pmb_size_valid(span)) {
+ newsize = span;
+ depth = i;
+ }
+
+ /* This is the end of the line.. */
+ if (!tail->link)
+ break;
- applied++;
+ tail = tail->link;
+ i++;
}
- return (applied == 0);
+ /*
+ * The merged page size must be valid.
+ */
+ if (!pmb_size_valid(newsize))
+ return;
+
+ head->flags &= ~PMB_SZ_MASK;
+ head->flags |= pmb_size_to_flags(newsize);
+
+ head->size = newsize;
+
+ __pmb_unmap_entry(head->link, depth);
+ __set_pmb_entry(head);
}
-int pmb_init(void)
+static void __init pmb_coalesce(void)
{
- int ret;
+ unsigned long flags;
+ int i;
+
+ write_lock_irqsave(&pmb_rwlock, flags);
+
+ for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+ struct pmb_entry *pmbe;
- jump_to_uncached();
+ if (!test_bit(i, pmb_map))
+ continue;
+
+ pmbe = &pmb_entry_list[i];
+
+ /*
+ * We're only interested in compound mappings
+ */
+ if (!pmbe->link)
+ continue;
+
+ /*
+ * Nothing to do if it already uses the largest possible
+ * page size.
+ */
+ if (pmbe->size == SZ_512M)
+ continue;
+
+ pmb_merge(pmbe);
+ }
+
+ write_unlock_irqrestore(&pmb_rwlock, flags);
+}
+
+#ifdef CONFIG_UNCACHED_MAPPING
+static void __init pmb_resize(void)
+{
+ int i;
/*
- * Sync our software copy of the PMB mappings with those in
- * hardware. The mappings in the hardware PMB were either set up
- * by the bootloader or very early on by the kernel.
+ * If the uncached mapping was constructed by the kernel, it will
+ * already be a reasonable size.
*/
- ret = pmb_synchronize_mappings();
- if (unlikely(ret == 0)) {
- back_to_cached();
- return 0;
+ if (uncached_size == SZ_16M)
+ return;
+
+ read_lock(&pmb_rwlock);
+
+ for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+ struct pmb_entry *pmbe;
+ unsigned long flags;
+
+ if (!test_bit(i, pmb_map))
+ continue;
+
+ pmbe = &pmb_entry_list[i];
+
+ if (pmbe->vpn != uncached_start)
+ continue;
+
+ /*
+ * Found it, now resize it.
+ */
+ spin_lock_irqsave(&pmbe->lock, flags);
+
+ pmbe->size = SZ_16M;
+ pmbe->flags &= ~PMB_SZ_MASK;
+ pmbe->flags |= pmb_size_to_flags(pmbe->size);
+
+ uncached_resize(pmbe->size);
+
+ __set_pmb_entry(pmbe);
+
+ spin_unlock_irqrestore(&pmbe->lock, flags);
}
- __raw_writel(0, PMB_IRMCR);
+ read_lock(&pmb_rwlock);
+}
+#endif
- /* Flush out the TLB */
- __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
+void __init pmb_init(void)
+{
+ /* Synchronize software state */
+ pmb_synchronize();
- back_to_cached();
+ /* Attempt to combine compound mappings */
+ pmb_coalesce();
- return 0;
+#ifdef CONFIG_UNCACHED_MAPPING
+ /* Resize initial mappings, if necessary */
+ pmb_resize();
+#endif
+
+ /* Log them */
+ pmb_notify();
+
+ writel_uncached(0, PMB_IRMCR);
+
+ /* Flush out the TLB */
+ __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
+ ctrl_barrier();
}
bool __in_29bit_mode(void)
if (state.event == PM_EVENT_ON &&
prev_state.event == PM_EVENT_FREEZE) {
struct pmb_entry *pmbe;
+
+ read_lock(&pmb_rwlock);
+
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
if (test_bit(i, pmb_map)) {
pmbe = &pmb_entry_list[i];
set_pmb_entry(pmbe);
}
}
+
+ read_unlock(&pmb_rwlock);
}
+
prev_state = state;
+
return 0;
}
git.openpandora.org / pandora-kernel.git / blobdiff